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91.发明授权Using UV/VIS spectrophotometry to regulate developer solution during a development process 失效在开发过程中使用UV / VIS分光光度法来调节显影剂溶液公开(公告)号：US06458607B1
公开(公告)日：2002-10-01
申请号：US09911151
申请日：2001-07-23
IPC分类号： H01L2166
CPC分类号： H01L22/26
摘要： A system for regulating temperature of a developer is provided. The system includes a system for regulating in-situ developer temperature, comprising at least one lamp operative to heat a portion of a developer; a lamp driving system for driving the at least one lamp; a system for directing radiation to the portion of the developer; a measuring system comprising a UV/Vis spectrophotometry system for measuring parameters of the developer based on radiation reflected from the developer; and a processor operatively coupled to the measuring system and a lamp driving system, the processor receiving developer parameter data from the measuring system and the processor using the data to at least partially base control of the at least one lamp so as to regulate temperature of at least a portion of the developer
摘要翻译： 提供了一种用于调节显影剂温度的系统。 该系统包括用于调节原位显影剂温度的系统，其包括至少一个用于加热显影剂的一部分的灯; 用于驱动所述至少一个灯的灯驱动系统; 用于将辐射引导到显影剂的一部分的系统; 包括用于基于从显影剂反射的辐射来测量显影剂的参数的UV / Vis分光光度测量系统的测量系统; 以及可操作地耦合到所述测量系统和灯驱动系统的处理器，所述处理器从所述测量系统接收显影剂参数数据和所述处理器，所述处理器使用所述数据至少部分地对所述至少一个灯的控制进行基准，以便调节所述至少一个灯的温度 至少一部分开发商
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公开(公告)号：US06372614B1
公开(公告)日：2002-04-16
申请号：US09861748
申请日：2001-05-19
IPC分类号： H01L214763
摘要： A dual damascene process and structure for fabricating semiconductor devices are disclosed. In one embodiment of the invention, a protection layer is deposited on top of a metal layer to protect the metal layer during subsequent etching of an oxide layer to form the via and damascene trench. Because the selectivity between the oxide layer and the protection layer is high, the number and complexity of processing steps are thereby reduced. Other embodiments of the present invention use a metal sealant layer and/or anti-reflective coating in conjunction with the protection layer in a dual-damascene process.
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93.发明授权Resist developer saving system using material to reduce surface tension and wet resist surface 有权抵抗使用材料的显影剂储存系统，以减少表面张力和抗湿表面公开(公告)号：US06251570B1
公开(公告)日：2001-06-26
申请号：US09604372
申请日：2000-06-27
IPC分类号： G03F732
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving the steps of exposing the semiconductor structure including the resist to acting radiation; contacting the semiconductor structure including the exposed resist with a solution comprising water and from about 0.01% to about 5% by weight of a surfactant; and developing the resist with a developer.
摘要翻译： 在一个实施例中，本发明涉及一种处理包括其上的抗蚀剂的半导体结构的方法，包括将包括抗蚀剂的半导体结构暴露于作用辐射的步骤; 将包含曝光的抗蚀剂的半导体结构与包含水和约0.01重量％至约5重量％的表面活性剂的溶液接触; 并用开发商开发抗蚀剂。
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94.发明授权Resist developer saving system using material to reduce surface tension and wet resist surface 有权抵抗使用材料的显影剂储存系统，以减少表面张力和抗湿表面
公开(公告)号：US6136514A
公开(公告)日：2000-10-24
申请号：US494699
申请日：2000-01-31
摘要： In one embodiment, the present invention relates to a method of processing a semiconductor structure including a resist thereon, involving the steps of exposing the semiconductor structure including the resist to actinic radiation; contacting the semiconductor structure including the exposed resist with a solution comprising water and from about 0.01% to about 5% by weight of a surfactant; and developing the resist with a developer.
摘要翻译： 在一个实施例中，本发明涉及一种处理包括其上的抗蚀剂的半导体结构的方法，包括将包括抗蚀剂的半导体结构暴露于光化辐射的步骤; 将包含曝光的抗蚀剂的半导体结构与包含水和约0.01重量％至约5重量％的表面活性剂的溶液接触; 并用开发商开发抗蚀剂。
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95.发明授权Reducing resist residue defects in open area on patterned wafer using trim mask 有权使用修剪掩模减少图案化晶片上的开放区域中的抗蚀剂残留缺陷公开(公告)号：US06613500B1
公开(公告)日：2003-09-02
申请号：US09824079
申请日：2001-04-02
IPC分类号： G03F700
CPC分类号： G03F7/70425 , G03F7/2022 , G03F7/203 , G03F7/70466
摘要： One aspect of the present invention relates to a method for reducing resist residue defects on a wafer structure. The method involves providing a semiconductor structure having a photoresist, the photoresist comprising open areas and circuit areas thereon; irradiating the open areas and circuit areas through a first photomask with a first energy dose to effect an image-wise pattern in the photoresist; irradiating the open areas of the photoresist through a second photomask with a second energy dose; and developing the photoresist.
摘要翻译： 本发明的一个方面涉及减少晶片结构上的抗蚀剂残留缺陷的方法。 该方法包括提供具有光致抗蚀剂的半导体结构，光致抗蚀剂包括开放区域和其上的电路区域; 通过具有第一能量剂量的第一光掩模照射开放区域和电路区域以在光致抗蚀剂中实现成像图案; 通过具有第二能量剂量的第二光掩模照射光致抗蚀剂的开放区域; 并显影光致抗蚀剂。
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公开(公告)号：US06845345B1
公开(公告)日：2005-01-18
申请号：US09777435
申请日：2001-02-06
IPC分类号： G06F11/00
CPC分类号： G05B23/0283
摘要： A system for analyzing diagnostic information associated with a spin track is provided. The system includes one or more analysis systems that collect diagnostic information from one or more spin tracks. The system further includes one or more maintenance systems that schedule routine and/or special maintenance based on analysis of the diagnostic information. An alternative aspect of the system further includes one or more control information systems that generate of feedback control information employed in adapting the processes performed by the spin track.
摘要翻译： 提供了一种用于分析与自旋轨迹相关联的诊断信息的系统。 该系统包括从一个或多个自旋轨道收集诊断信息的一个或多个分析系统。 该系统还包括一个或多个维护系统，其基于对诊断信息的分析来调度例行和/或特殊维护。 该系统的另一方面还包括一个或多个控制信息系统，其产生用于适应由旋转轨迹执行的处理的反馈控制信息。
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公开(公告)号：US06545753B2
公开(公告)日：2003-04-08
申请号：US09893186
申请日：2001-06-27
IPC分类号： G01N2100
CPC分类号： H01L21/7681 , G01N21/4738 , H01J37/32935
摘要： A system for monitoring and/or controlling an etch process associated with a dual damascene process via scatterometry based processing is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the etch results achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the desirability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor produces a real time feed forward information to control the etch process, in particular, terminating the etch process when desired end points have been encountered.
摘要翻译： 提供了一种用于通过基于散射测量的处理来监测和/或控制与双镶嵌工艺相关联的蚀刻工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。 从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。 所收集的光指示在晶片的各个部分实现的蚀刻结果。 测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可取性。 该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。 处理器产生实时前馈信息以控制蚀刻工艺，特别是在遇到所需端点时终止蚀刻工艺。
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公开(公告)号：US06354133B1
公开(公告)日：2002-03-12
申请号：US09729293
申请日：2000-12-04
IPC分类号： G01B528
CPC分类号： G01Q40/02 , G01Q40/00 , Y10S977/742 , Y10S977/842 , Y10S977/849 , Y10S977/85 , Y10S977/876 , Y10S977/901
摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.
摘要翻译： 本发明提供了用于校准纳米测量装置的系统，方法和标准。 本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。 碳纳米管校准标准品的宽度以高精度已知。 考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。 本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。
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公开(公告)号：US06828162B1
公开(公告)日：2004-12-07
申请号：US09894434
申请日：2001-06-28
IPC分类号： H01L2100
CPC分类号： H01L21/67253 , G01N21/4738 , H01L21/02129 , H01L21/31625
摘要： A system for monitoring and controlling a boron phosphorous doped silicon oxide (BPSG) deposition and reflow process is provided. The system includes one or more light sources, each light source directing light to one or more portions of a wafer upon which BPSG is deposited. Light reflected from the BPSG is collected by a measuring system, which processes the collected light. Light passing through the BPSG may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the conformality of the BPSG deposition of the respective portions of the wafer. The measuring system provides BPSG deposition related data to a processor that determines the BPSG deposition of the respective portions of the wafer. The system also includes a plurality of reflow controlling devices, each such device corresponding to a respective portion of the wafer and providing for the heating and/or cooling thereof. The processor selectively controls the reflow controlling devices so as to regulate temperature of the respective portions of the wafer.
摘要翻译： 提供了一种用于监测和控制硼磷掺杂氧化硅（BPSG）沉积和回流工艺的系统。 该系统包括一个或多个光源，每个光源将光引导到沉积BPSG的晶片的一个或多个部分。 从BPSG反射的光被测量系统收集，该系统处理收集的光。 通过BPSG的光可以类似地由处理所收集的光的测量系统收集。 所收集的光表示晶片的各个部分的BPSG沉积的一致性。 测量系统将BPSG沉积相关数据提供给确定晶片各部分的BPSG沉积的处理器。 该系统还包括多个回流控制装置，每个这样的装置对应于晶片的相应部分并提供加热和/或冷却。 处理器选择性地控制回流控制装置，以便调节晶片各部分的温度。
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公开(公告)号：US06562248B1
公开(公告)日：2003-05-13
申请号：US09817518
申请日：2001-03-26
IPC分类号： G01N2100
摘要： A system for monitoring and controlling aperture etching in a complimentary phase shift mask is provided. The system includes one or more light sources, each light source directing light to one or more apertures etched on a mask. Light reflected from the apertures is collected by a measuring system, which processes the collected light. Light passing through the apertures may similarly be collected by the measuring system, which processes the collected light. The collected light is indicative of the depth and/or width of the openings on the mask. The measuring system provides depth and/or width related data to a processor that determines the acceptability of the aperture depth and/or width. The system also includes a plurality of etching devices associated with etching apertures in the mask. The processor selectively controls the etching devices so as to regulate aperture etching.
摘要翻译： 提供了一种用于在补偿相移掩模中监测和控制孔蚀刻的系统。 该系统包括一个或多个光源，每个光源将光引导到在掩模上蚀刻的一个或多个孔。 从孔径反射的光由测量系统收集，该系统处理所收集的光。 通过孔的光可以类似地由处理收集的光的测量系统收集。 收集的光指示掩模上的开口的深度和/或宽度。 测量系统向确定孔径深度和/或宽度的可接受性的处理器提供深度和/或宽度相关数据。 该系统还包括与掩模中的孔蚀刻相关联的多个蚀刻装置。 处理器选择性地控制蚀刻装置以调节孔径蚀刻。
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