公开(公告)号：US20140379773A1

公开(公告)日：2014-12-25

申请号：US13926175

申请日：2013-06-25

申请人： Simon Rubanovich ,  Thierry Pons ,  Amit Gradstein ,  Zeev Sperber

发明人： Simon Rubanovich ,  Thierry Pons ,  Amit Gradstein ,  Zeev Sperber

IPC分类号： G06F7/483 ,  G06F7/485 ,  G06F7/487

CPC分类号： G06F7/483 ,  G06F7/5443 ,  G06F7/764

摘要： Systems and methods of performing a fused multiply add (FMA) operations are provided. In one embodiment, the length of the adder used by the FMA operation is less than 3*N, where N is the number of bits in the mantissa term of a floating point number. A mask may be used to perform the addition portion of the FMA operation using the adder. A second mask may be used to denormalize the result of the addition portion of the FMA operation if an underflow occurs.

摘要翻译： 提供了执行融合乘法（FMA）操作的系统和方法。 在一个实施例中，由FMA操作使用的加法器的长度小于3 * N，其中N是浮点数的尾数项中的位数。 可以使用掩码来使用加法器来执行FMA操作的相加部分。 如果发生下溢，则可以使用第二掩模来对FMA操作的添加部分的结果进行非规范化。

公开(公告)号：US08879725B2

公开(公告)日：2014-11-04

申请号：US12040214

申请日：2008-02-29

申请人： Shay Gueron ,  Zeev Sperber

发明人： Shay Gueron ,  Zeev Sperber

IPC分类号： H04K1/00 ,  H04L9/32 ,  H04L9/06 ,  G06F21/75

CPC分类号： H04L9/0681 ,  G06F9/30007 ,  G06F21/75 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

摘要： The Advanced Encryption Standard (AES) is a symmetric block cipher that can encrypt and decrypt information. Encryption (cipher) performs a series of transformations (Shift Rows, Substitute Bytes, Mix Columns) using the secret key (cipher key) to transforms intelligible data referred to as “plaintext” into an unintelligible form referred to as “cipher text”. The transformations (Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) in the inverse cipher (decryption) are the inverse of the transformations in the cipher. Encryption and decryption is performed efficiently through the use of instructions that perform the series of transformations. Combinations of these instructions allow the isolation of the transformations (Shift Rows, Substitute Bytes, Mix Columns, Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) to be obtained.

摘要翻译： 高级加密标准（AES）是可以加密和解密信息的对称块密码。 加密（密码）使用秘密密钥（密码密钥）执行一系列转换（Shift Rows，Substitute Bytes，Mix Columns），将被称为“明文”的可理解数据转换成称为“密文”的无法理解的形式。 反密码（解密）中的变换（逆位排，逆替换字节，反混合列）是密码中的变换的逆。 通过使用执行一系列转换的指令来有效地执行加密和解密。 这些指令的组合允许要获得的转换的隔离（Shift Rows，Substitution Bytes，Mix Columns，Inverse Shift Rows，Inverse Substitute Bytes，Inverse Mix Columns）。

公开(公告)号：US20130046960A1

公开(公告)日：2013-02-21

申请号：US13656636

申请日：2012-10-19

申请人： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

发明人： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC分类号： G06F9/30

CPC分类号： G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

公开(公告)号：US20130046959A1

公开(公告)日：2013-02-21

申请号：US13656634

申请日：2012-10-19

申请人： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

发明人： Rajiv Kapoor ,  Ronen Zohar ,  Mark Buxton ,  Zeev Sperber ,  Koby Gottlieb

IPC分类号： G06F9/30

CPC分类号： G06F9/30021 ,  G06F7/026 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30094 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3887 ,  G06F12/0875 ,  G06F2212/452

摘要： A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

摘要翻译： 一种用于在处理器中包括用于对打包或未打包的数据执行逻辑比较和分支支持操作的指令的方法和装置。 在一个实施例中，指令解码逻辑解码用于执行单元对包括逻辑比较的打包数据元素进行操作的指令。 包括128位打包数据寄存器的寄存器文件存储打包的单精度浮点数（SPFP）和压缩整数数据元素。 逻辑比较可以包括SPFP数据元素的比较和整数数据元素的比较，并且设置至少一个位以指示结果。 基于这些比较，采取分支支持行动。 这种分支支持动作可以包括设置至少一个比特，响应于分支指令又可以由分支单元利用该比特。 或者，分支支持动作可以包括分支到指示的目标代码位置。

公开(公告)号：US07921280B2

公开(公告)日：2011-04-05

申请号：US12215526

申请日：2008-06-27

申请人： Zeev Sperber ,  Rafi Marom ,  Ofer Levy

发明人： Zeev Sperber ,  Rafi Marom ,  Ofer Levy

IPC分类号： G06F9/30

CPC分类号： G06F1/3203 ,  G06F1/3287 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  Y02D10/124 ,  Y02D10/171 ,  Y02D50/20

摘要： In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated with an executed instruction if information associated with the executed instruction is stored in an on-demand portion of at least one of arrays. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，本发明包括用于接收和退出执行的指令的退休单元。 退休单元可以包括用于在分配时接收信息的第一阵列和用于在执行之后接收信息的第二阵列。 如果与所执行的指令相关联的信息被存储在阵列中的至少一个的按需部分中，退休单元还可以包括用于计算与执行的指令相关联的事件的逻辑。 描述和要求保护其他实施例。

公开(公告)号：US07721076B2

公开(公告)日：2010-05-18

申请号：US11641424

申请日：2006-12-18

申请人： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

发明人： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

IPC分类号： G06F9/00

CPC分类号： G06F9/3865 ,  G06F9/3857

摘要： Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an out-of-order processor. Dispatched instructions (or micro-ops) may be maintained in a queue, such as a reorder buffer (ROB), for in-order retirement. For at least one embodiment, event information is maintained only in the register and is not maintained in a ROB. For at least one other embodiment, event information is maintained in a ROB entry for some events and in the register for others. For such latter embodiment, a retire engine takes the contents of both the ROB entry and the register into account when determining whether to take an exception or otherwise initiate a handling sequence during in-order instruction retirement. Other embodiments are also described and claimed.

摘要翻译： 方法，装置和系统实施例提供了一个寄存器来跟踪处理器中最旧的异常事件或粘性事件。 处理器可以是乱序处理器。 调度的指令（或微操作）可以被维护在队列中，例如重新排序缓冲器（ROB），用于按顺序退出。 对于至少一个实施例，事件信息仅在寄存器中被维护，并且不保持在ROB中。 对于至少一个其他实施例，事件信息在一些事件的ROB条目中以及在其他的注册中保持。 对于这样的后一个实施例，退休引擎在确定是否采取异常或在按顺序指令退出时以其他方式启动处理顺序时考虑到ROB入口和寄存器两者的内容。 还描述和要求保护其他实施例。

公开(公告)号：US20090214026A1

公开(公告)日：2009-08-27

申请号：US12038071

申请日：2008-02-27

申请人： Shay Gueron ,  Amit Gradstein ,  Zeev Sperber

发明人： Shay Gueron ,  Amit Gradstein ,  Zeev Sperber

IPC分类号： H04L9/06

CPC分类号： H04L9/0631 ,  G06F9/30007 ,  H04L2209/125

摘要： The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by dispatching an AES round instruction in every cycle.

摘要翻译： 在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。 可以通过在每个周期中调度AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。

公开(公告)号：US07076614B2

公开(公告)日：2006-07-11

申请号：US09896234

申请日：2001-06-29

申请人： Zeev Sperber ,  Gabi Malka ,  Gilad Shmueli ,  Shmulik Branski

发明人： Zeev Sperber ,  Gabi Malka ,  Gilad Shmueli ,  Shmulik Branski

IPC分类号： G06F12/00

CPC分类号： G06F13/161 ,  G09G5/39

摘要： A system and method of optimizing system memory bus bandwidth in a computer system. The system prepares to receive first data from system memory in accordance with at least one read request by evicting previously stored second data to a write back buffer. The at least one read request is then issued consecutively to system memory via the system memory bus. After issuance of the at least one read request, at least one write request is issued consecutively to send the second data in the write back buffer to the system memory via the system memory bus. The consecutive issuance of read and write requests avoids read-to-write and write-to-read bubbles that occur when alternating read and write requests are issued to system memory.

摘要翻译： 一种在计算机系统中优化系统内存总线带宽的系统和方法。 根据至少一个读取请求，系统准备从系统存储器接收第一数据，通过将先前存储的第二数据驱逐到回写缓冲器。 然后，至少一个读请求经由系统存储器总线连续地发送到系统存储器。 在发出至少一个读取请求之后，连续发出至少一个写入请求，以经由系统存储器总线将写入缓冲器中的第二数据发送到系统存储器。 读取和写入请求的连续发送避免了在将读写请求交给系统内存时发生的读写写入和写入读取的气泡。

公开(公告)号：US20060095731A1

公开(公告)日：2006-05-04

申请号：US10932088

申请日：2004-09-02

申请人： Yuval Bustan ,  Asi Joseph ,  Guillermo Savransky ,  Zeev Sperber

发明人： Yuval Bustan ,  Asi Joseph ,  Guillermo Savransky ,  Zeev Sperber

IPC分类号： G06F9/30

CPC分类号： G06F9/3836 ,  G06F9/3017 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： An out-of-order subsystem of a processor includes a register alias table and allocation (RAT/ALLOC) unit, a reservation station (RS) and a reorder buffer (ROB). Destination identifiers of one or more execution results that are not yet stored in any register file of the ROB may be compared to source identifiers of operands of micro-operations that are being issued to the RS. Each execution result corresponding to a destination identifier that matches one of the source identifiers is retrieved from a data path external to the ROB and routed to an appropriate port of the RS for an operand corresponding to the source identifier so that the RAT/ALLOC unit does not need to allocate a read port of the ROB for the RS to read the execution result.

摘要翻译： 处理器的乱序子系统包括寄存器别名表和分配（RAT / ALLOC）单元，保留站（RS）和重排序缓冲器（ROB）。 还没有存储在ROB的任何寄存器文件中的一个或多个执行结果的目的地标识符可以与正在发布到RS的微操作的操作数的源标识符进行比较。 对应于与源标识符之一匹配的目的地标识符的每个执行结果从ROB外部的数据路径检索，并被路由到与源标识符相对应的操作数的RS的适当端口，使得RAT / ALLOC单元 不需要分配ROB的读端口来读取执行结果。

公开(公告)号：US06557083B1

公开(公告)日：2003-04-29

申请号：US09608787

申请日：2000-06-30

申请人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

发明人： Zeev Sperber ,  Guy Peled ,  Doron Orenstein ,  Ehud Cohen ,  Gabi Malka

IPC分类号： G06F1210

CPC分类号： G06F12/0875 ,  G06F12/1054 ,  G06F2212/401

摘要： A memory system is provided for storing multiple data types. The memory system includes a main memory, a local cache, and a translation unit. The local cache has multiple entries, each of which includes a data field to store data and a status field to indicate a storage state for the stored data. The translation unit includes a translation lookaside buffer (TLB) and a status-cache (STC). The TLB stores address translations for data in the main memory, and the STC stores storage states for data indicated by the address translations.