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    System and method for managing peak power demand and noise in non-volatile memory array
    91.
    发明授权
    System and method for managing peak power demand and noise in non-volatile memory array 有权

    公开(公告)号：US10580491B2

    公开(公告)日：2020-03-03

    申请号：US16015020

    申请日：2018-06-21

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Vipin Tiwari ,  Hieu Van Tran ,  Nhan Do ,  Mark Reiten

    IPC: G11C5/08 ,  G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/423

    Abstract: A memory device includes rows and columns of memory cells, word lines each connected to a memory cell row, bit lines each connected to a memory cell column, a word line driver connected to the word lines, a bit line driver connected to the bit lines, word line switches each disposed on one of the word lines for selectively connecting one memory cell row to the word line driver, and bit line switches each disposed on one of the bit lines for selectively connecting one memory cell column to the bit line driver. A controller controls the word line switches to connect only some of the rows of memory cells to the word line driver at a first point in time, and controls the bit line switches to connect only some of the columns of memory cells to the bit line driver at a second point in time.

    Split-Gate Flash Memory Array With Byte Erase Operation
    93.
    发明申请
    Split-Gate Flash Memory Array With Byte Erase Operation 审中-公开

    公开(公告)号：US20190355424A1

    公开(公告)日：2019-11-21

    申请号：US16042000

    申请日：2018-07-23

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hsuan Liang ,  Jeng-Wei Yang ,  Man-Tang Wu ,  Nhan Do ,  Hieu Van Tran

    IPC: G11C16/16 ,  G11C16/04

    Abstract: A memory device with memory cells in rows and columns, word lines connecting together the control gates for the memory cell rows, bit lines electrically connecting together the drain regions for the memory cell columns, first sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a first plurality of memory cell columns, second sub source lines each electrically connecting together the source regions in one of the memory cell rows and in a second plurality of memory cell columns, first and second source lines, first select transistors each connected between one of first sub source lines and the first source line, second select transistors each connected between one of second sub source lines and the second source line, and select transistor lines each connected to gates of one of the first select transistors and one of the second select transistors.

    Virtual Ground Non-volatile Memory Array
    96.
    发明申请
    Virtual Ground Non-volatile Memory Array 审中-公开

    公开(公告)号：US20190164984A1

    公开(公告)日：2019-05-30

    申请号：US16264349

    申请日：2019-01-31

    Applicant: Silicon Storage Technology, Inc

    Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Nhan Do

    IPC: H01L27/11526 ,  H01L29/788 ,  H01L29/423 ,  G11C16/14 ,  G11C16/04 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/11519

    Abstract: A memory device with memory cell pairs each having a single continuous channel region, first and second floating gates over first and second portions of the channel region, an erase gate over a third portion of the channel region between the first and second channel region portions, and first and second control gates over the first and second floating gates. For each of the pairs of memory cells, the first region is electrically connected to the second region of an adjacent pair of memory cells in the same active region, and the second region is electrically connected to the first region of an adjacent pair of the memory cells in the same active region.

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