公开(公告)号：US07596148B2

公开(公告)日：2009-09-29

申请号：US11786275

申请日：2007-04-11

申请人： Manu Gulati ,  Laurent R. Moll ,  James B. Keller

发明人： Manu Gulati ,  Laurent R. Moll ,  James B. Keller

IPC分类号： H04L12/28

CPC分类号： G06F13/4247

摘要： A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

摘要翻译： 用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段，其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段，并且其中数据段 所述多个数据段对应于所述多路复用数据片段中的一个。 该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。 该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。 该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

公开(公告)号：US07069361B2

公开(公告)日：2006-06-27

申请号：US09840449

申请日：2001-04-23

申请人： Jonathan M. Owen ,  Mark D. Hummel ,  Derrick R. Meyer ,  James B. Keller

发明人： Jonathan M. Owen ,  Mark D. Hummel ,  Derrick R. Meyer ,  James B. Keller

IPC分类号： G06F13/00

CPC分类号： H04L1/1671

摘要： A method and system of expediting issuance of a second request of a pair of ordered requests into a distributed coherent communication fabric. The first request of the ordered pair is issued into the coherent communication fabric and directed to a first target. Issuance of the second request into the coherent communication fabric is stalled until the first target receives and orders the first request and transmits a response acknowledging the same.

公开(公告)号：US06965973B2

公开(公告)日：2005-11-15

申请号：US10269827

申请日：2002-10-11

申请人： Joseph B. Rowlands ,  James B. Keller

发明人： Joseph B. Rowlands ,  James B. Keller

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0817 ,  Y10S707/99952

摘要： A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.

摘要翻译： 耦合节点以接收相关命令并耦合到存储器，其中节点包括被配置为跟踪小于存储器中的一致性块的总数的第一数量的一致性块的状态的目录。 该目录被配置为响应于一致性命令来分配第一条目以跟踪第一一致性块的状态。 如果第一条目当前正在跟踪第二相关块的状态，则第二节点被配置为生成一个或多个相关命令以使多个节点中的第二一致性块无效。

公开(公告)号：US06748479B2

公开(公告)日：2004-06-08

申请号：US10270029

申请日：2002-10-11

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F1300

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US06748442B1

公开(公告)日：2004-06-08

申请号：US09477125

申请日：2000-01-03

申请人： James B. Keller

发明人： James B. Keller

IPC分类号： G06F1516

CPC分类号： G06F13/4217

摘要： A computer system has a communication link that includes a control signal and data lines. A first control packet having a-plurality of bytes is transferred over the data lines from a first to a second node on the communication link. The control line is asserted to indicate transfer of a control packet. After transfer of the first control packet, a first portion of a multi-byte data packet associated with the first control packet is transferred with the control line deasserted. During transfer of the data packet the control line is asserted and transfer of the data packet is suspended. A second control packet is then transferred over the data lines. Subsequent to transferring the second control packet, the remainder of the data packet is transferred with the control line deasserted.

摘要翻译： 计算机系统具有包括控制信号和数据线的通信链路。 具有多个字节的第一控制分组通过数据线从通信链路上的第一节点传送到第二节点。 控制线被断言以指示控制分组的传送。 在传送第一控制分组之后，与控制线无关地传送与第一控制分组相关联的多字节数据分组的第一部分。 在传输数据包的过程中，控制线被断言，数据包的传输被暂停。 然后通过数据线传输第二个控制数据包。 在传送第二控制分组之后，数据分组的其余部分被控制线断言传送。

公开(公告)号：US06714994B1

公开(公告)日：2004-03-30

申请号：US09429118

申请日：1999-10-27

申请人： James B. Keller ,  Derrick R. Meyer

发明人： James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F300

CPC分类号： G06F13/1621 ,  G06F13/405 ,  G06F15/17381

摘要： A computer system is presented which implements a system and method for conveying packets between a coherent processing subsystem and a non-coherent input/output (I/O) subsystem. The processing subsystem includes a first processing node coupled to a second processing node via a coherent communication link. The first processing node includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. The I/O subsystem includes an I/O node coupled to the first processing node via a non-coherent communication link. The I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The coherent and non-coherent communication links are physically identical. For example, the coherent and non-coherent communication links may have the same electrical interface and the same signal definition. The host bridge translates non-coherent packets from the I/O node to coherent packets, and transmits the coherent packets to the second processing node. The host bridge also translates coherent packets from the second processing node to non-coherent packets, and transmits the non-coherent packets to the I/O node. The coherent and non-coherent packets have identically located command fields. The translating process includes copying the contents of the command field of one packet type to the command field of the other packet type.

摘要翻译： 提出了一种实现用于在相干处理子系统和非相干输入/输出（I / O）子系统之间传送分组的系统和方法的计算机系统。 处理子系统包括经由相干通信链路耦合到第二处理节点的第一处理节点。 第一处理节点包括主转换台，其转换在处理子系统和I / O子系统之间移动的分组。 I / O子系统包括经由非相干通信链路耦合到第一处理节点的I / O节点。 I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 相干和非相干的通信链路在物理上是相同的。 例如，相干和非相干通信链路可以具有相同的电接口和相同的信号定义。 主机桥将非相干分组从I / O节点转换为相关分组，并将相干分组发送到第二处理节点。 主桥还将来自第二处理节点的相干分组转换为非相干分组，并将非相干分组发送到I / O节点。 相干和非相干数据包具有相同的命令字段。 翻译处理包括将一个分组类型的命令字段的内容复制到另一个分组类型的命令字段。

公开(公告)号：US06704854B1

公开(公告)日：2004-03-09

申请号：US09433185

申请日：1999-10-25

申请人： Stephan G. Meier ,  James B. Keller

发明人： Stephan G. Meier ,  James B. Keller

IPC分类号： G06F930

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3885

摘要： A processor includes execution resources for handling a first memory operation and a concurrent second memory operation. If one of the memory operations is misaligned, the processor may allocate the execution resources for the other memory operation to that memory operation. In one embodiment, the older memory operation proceeds if misalignment is detected. The younger memory operation is retried and may be reexecuted at a later time. If the older memory operation is misaligned, the execution resources provided for the younger operation may be allocated to the older memory operation. If only the younger memory operation is misaligned, the younger memory operation may be the older memory operation during a subsequent reexecution and may thus be allocated the execution resources to allow the memory operation to complete.

摘要翻译： 处理器包括用于处理第一存储器操作和并行第二存储器操作的执行资源。 如果其中一个存储器操作未对准，则处理器可以将该另一存储器操作的执行资源分配给该存储器操作。 在一个实施例中，如果检测到未对准，则旧的存储器操作进行。 较年轻的内存操作被重试，可能会在以后重新执行。 如果较旧的内存操作未对齐，则为年轻操作提供的执行资源可能会分配给较旧的内存操作。 如果仅较年轻的存储器操作未对准，则较小的存储器操作可能是在随后的重新执行期间较旧的存储器操作，因此可以分配执行资源以允许存储器操作完成。

公开(公告)号：US06633936B1

公开(公告)日：2003-10-14

申请号：US09670362

申请日：2000-09-26

申请人： James B. Keller ,  Chun H. Ning ,  Kwong-Tak A. Chui ,  Mark D. Hayter

发明人： James B. Keller ,  Chun H. Ning ,  Kwong-Tak A. Chui ,  Mark D. Hayter

IPC分类号： G06F1300

CPC分类号： G06F13/161

摘要： An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected.

摘要翻译： 自适应重试机制可以记录近期事务的延迟（例如，第一数据传输等待时间），并且可以从两个或更多个重试延迟中选择重试延迟。 重试延迟可以用于事务，并且可以在事务中指定在第一数据传送尚未发生的情况下重试事务的时间点。 在一个实现中，该重试延迟集合包括最小重试延迟，标称重试延迟和最大重试延迟。 标称重试延迟可以被设置为略大于系统中事务的预期等待时间。 最小重试延迟可能小于标称重试延迟，并且最大重试延迟可能大于标称重试延迟。 如果正在经历大于标称重试延迟但小于最大重试延迟的延迟，则可以选择最大重试延迟。 另一方面，如果正在经历大于最大重试延迟的延迟，则可以选择最小重试延迟。

公开(公告)号：US06631401B1

公开(公告)日：2003-10-07

申请号：US09217367

申请日：1998-12-21

申请人： James B. Keller ,  Dale E. Gulick

发明人： James B. Keller ,  Dale E. Gulick

IPC分类号： G06F15167

CPC分类号： G06F12/0815 ,  G06F12/0817

摘要： A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data). On the other hand, for write transactions (in which data is being updated in memory at the target node of the transaction), the probe commands may specify the target of the transaction as the receiving node. In this manner, the target may determine when to commit the write data to memory and may receive any dirty data to be merged with the write data.

摘要翻译： 计算机系统可以包括多个处理节点，其中的一个或多个处理节点可以耦合到可以形成分布式存储器系统的分离的存储器。 处理节点可以包括高速缓存，并且计算机系统可以保持高速缓存和分布式存储器系统之间的一致性。 特别地，计算机系统可以实现灵活的探测命令/响应路由方案。 该方案可以采用探测命令中的指示，该指示标识接收节点以接收探测响应。 例如，可以包括指示目标或事务源应该接收对应于事务的探测响应的探测命令。 探测命令可以将事务的来源指定为读取事务的接收节点（使得脏数据从存储脏数据的节点传送到源节点）。 另一方面，对于写入事务（其中数据正在事务的目标节点的存储器中更新），探测命令可以将事务的目标指定为接收节点。 以这种方式，目标可以确定何时将写入数据提交到存储器，并且可以接收要与写入数据合并的任何脏数据。

公开(公告)号：US06490661B1

公开(公告)日：2002-12-03

申请号：US09217212

申请日：1998-12-21

申请人： James B. Keller ,  Derrick R. Meyer

发明人： James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F1314

CPC分类号： G06F12/0813

摘要： A messaging scheme that accomplishes cache-coherent data transfers during a memory read operation in a multiprocessing computer system is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and by causing the node having an updated copy of the cache block to send the cache block to the source node. Each processing node that receives a probe command sends, in return, a probe response indicating whether that processing node has a cached copy of the data and the state of the cached copy if the responding node has the cached copy. The target node sends a read response including the requested data to the source node. The source node waits for responses from the target node and from each of the remaining node in the system and acknowledges the receipt of requested data by sending a source done response to the target node.

摘要翻译： 描述了在多处理计算机系统中的存储器读取操作期间实现高速缓存相干数据传输的消息传递方案。 源处理节点向目标处理节点发送读命令，以从与目标处理节点相关联的系统存储器中的指定存储器位置读取数据。 响应于读取命令，目标处理节点向计算机系统中的所有其余处理节点发送探测命令，而不管剩余节点中的一个或多个是否具有高速缓存在其各自高速缓冲存储器中的数据的副本。 Probe命令通过适当地改变包含所请求数据的缓存块的状态，并使得具有高速缓存块的更新副本的节点将高速缓存块发送到源节点，导致每个节点维持高速缓存一致性。 接收探测命令的每个处理节点作为回报发送指示该处理节点是否具有数据的缓存副本的探测响应以及响应节点是否具有缓存副本的缓存副本的状态。 目标节点将包含请求的数据的读取响应发送到源节点。 源节点等待来自目标节点和系统中的每个剩余节点的响应，并通过向目标节点发送源完成响应来确认所请求数据的接收。