公开(公告)号：US06704854B1

公开(公告)日：2004-03-09

申请号：US09433185

申请日：1999-10-25

申请人： Stephan G. Meier ,  James B. Keller

发明人： Stephan G. Meier ,  James B. Keller

IPC分类号： G06F930

CPC分类号： G06F9/3836 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3885

摘要： A processor includes execution resources for handling a first memory operation and a concurrent second memory operation. If one of the memory operations is misaligned, the processor may allocate the execution resources for the other memory operation to that memory operation. In one embodiment, the older memory operation proceeds if misalignment is detected. The younger memory operation is retried and may be reexecuted at a later time. If the older memory operation is misaligned, the execution resources provided for the younger operation may be allocated to the older memory operation. If only the younger memory operation is misaligned, the younger memory operation may be the older memory operation during a subsequent reexecution and may thus be allocated the execution resources to allow the memory operation to complete.

摘要翻译： 处理器包括用于处理第一存储器操作和并行第二存储器操作的执行资源。 如果其中一个存储器操作未对准，则处理器可以将该另一存储器操作的执行资源分配给该存储器操作。 在一个实施例中，如果检测到未对准，则旧的存储器操作进行。 较年轻的内存操作被重试，可能会在以后重新执行。 如果较旧的内存操作未对齐，则为年轻操作提供的执行资源可能会分配给较旧的内存操作。 如果仅较年轻的存储器操作未对准，则较小的存储器操作可能是在随后的重新执行期间较旧的存储器操作，因此可以分配执行资源以允许存储器操作完成。

公开(公告)号：US06622235B1

公开(公告)日：2003-09-16

申请号：US09476204

申请日：2000-01-03

申请人： James B. Keller ,  Ramsey W. Haddad ,  Stephan G. Meier

发明人： James B. Keller ,  Ramsey W. Haddad ,  Stephan G. Meier

IPC分类号： G06F938

CPC分类号： G06F9/3861 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3859

摘要： A scheduler issues memory operations without regard to whether or not resources are available to handle each possible execution outcome of that memory operation. The scheduler also retains the memory operation after issuance. If a condition occurs which prevents correct execution of the memory operation, the memory operation is retried. The scheduler subsequently reschedules and reissues the memory operation in response to the retry. Additionally, the scheduler may receive a retry type indicating the reason for retry. Certain retry types may indicate a delayed reissuance of the memory operation until the occurrence of a subsequent event. In response to such retry types, the scheduler monitors for the subsequent event and delays reissuance until the event is detected. The scheduler may include a physical address buffer to detect a load memory operation which incorrectly issued prior to an older store memory operation upon which it is dependent for the memory operation. The scheduler may also include a store tag buffer to detect that a load memory operation is to be reissued due to the reissuance of a store memory operation on which the load was determined to be dependent during the previous execution of the load memory operation.

摘要翻译： 调度器发出存储器操作，而不考虑资源是否可用于处理该存储器操作的每个可能的执行结果。 调度程序也保留发行后的内存操作。 如果发生阻止正确执行存储器操作的条件，则重试存储器操作。 调度器随后重新调度并重新发出响应于重试的存储器操作。 此外，调度器可以接收指示重试原因的重试类型。 某些重试类型可能指示存储器操作的延迟重新发布，直到发生后续事件。 响应于这种重试类型，调度器监视后续事件并延迟重新发布，直到检测到事件。 调度器可以包括物理地址缓冲器，以检测在其依赖于存储器操作的较旧的存储存储器操作之前错误地发出的加载存储器操作。 调度器还可以包括存储标签缓冲器，以检测由于在先前执行加载存储器操作期间确定负载被确定为依赖的存储存储器操作的重新发布，将重新发布加载存储器操作。

公开(公告)号：US06542984B1

公开(公告)日：2003-04-01

申请号：US09476578

申请日：2000-01-03

申请人： James B. Keller ,  Ramsey W. Haddad ,  Stephan G. Meier

发明人： James B. Keller ,  Ramsey W. Haddad ,  Stephan G. Meier

IPC分类号： G06F1576

CPC分类号： G06F9/3861 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3859

摘要： A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be incorrectly executed, the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Furthermore, the scheduler may employ a more aggressive scheduling mechanism since the penalty for incorrect execution is reduced. Additionally, the scheduler maintains the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction operation are not reissued. Accordingly, the penalty for incorrect scheduling of instruction operations may be further decreased over the purging of the particular instruction and all younger instruction operations and refetching the particular instruction operation.

摘要翻译： 调度器执行指令操作，还保留指令操作。 如果随后发现特定的指令操作被错误地执行，则可以从调度器重新发出特定的指令操作。 与从流水线中清除特定的指令操作和更年轻的指令操作以及重新指定特定的指令操作相比，指令操作的不正确调度的惩罚可能会减少。 此外，调度器可以采用更积极的调度机制，因为减少了错误执行的惩罚。 此外，调度器维护已发出的每个指令操作的依赖指示。 如果重新发出特定的指令操作，则可以通过依赖指示来识别依赖于特定指令操作（直接或间接）的指令操作。 调度程序也重新发出相关的指令操作。 不按照程序顺序执行特定指令操作但不依赖于特定指令操作的指令操作不重新发行。 因此，可以通过清除特定指令和所有更年轻的指令操作并重新获取特定的指令操作来进一步减少对指令操作的不正确调度的惩罚。

公开(公告)号：US06564315B1

公开(公告)日：2003-05-13

申请号：US09476322

申请日：2000-01-03

申请人： James B. Keller ,  Ramsey W. Haddad ,  Stephan G. Meier

发明人： James B. Keller ,  Ramsey W. Haddad ,  Stephan G. Meier

IPC分类号： G06F9312

CPC分类号： G06F9/3842 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861

摘要： A scheduler issues instruction operations for execution, but also retains the instruction operations. If a particular instruction operation is subsequently found to be required to execute non-speculatively, the particular instruction operation is still stored in the scheduler. Subsequent to determining that the particular operation has become non-speculative (through the issuance and execution of instruction operations prior to the particular instruction operation), the particular instruction operation may be reissued from the scheduler. The penalty for incorrect scheduling of instruction operations which are to execute non-speculatively may be reduced as compared to purging the particular instruction operation and younger instruction operations from the pipeline and refetching the particular instruction operation. Additionally, the scheduler may maintain the dependency indications for each instruction operation which has been issued. If the particular instruction operation is reissued, the instruction operations which are dependent on the particular instruction operation (directly or indirectly) may be identified via the dependency indications. The scheduler reissues the dependent instruction operations as well. Instruction operations which are subsequent to the particular instruction operation in program order but which are not dependent on the particular instruction operation are not reissued. Accordingly, the penalty for incorrect scheduling of instruction operations which are to be executed non-speculatively may be further decreased over the purging of the particular instruction and all younger instruction operations and refetching the particular instruction operation.

摘要翻译： 调度器执行指令操作，还保留指令操作。 如果随后发现特定的指令操作被要求非推测地执行，则特定的指令操作仍然存储在调度器中。 在确定特定操作已经变得不推测（通过在特定指令操作之前发出和执行指令操作）之后，特定指令操作可以从调度器重新发行。 与从流水线中清除特定的指令操作和较年轻的指令操作以及重新指定特定的指令操作相比，与推测性地执行的指令操作的不正确调度的惩罚可能会减少。 此外，调度器可以维护已经发出的每个指令操作的依赖指示。 如果重新发出特定的指令操作，则可以通过依赖指示来识别依赖于特定指令操作（直接或间接）的指令操作。 调度程序也重新发出相关的指令操作。 不按照程序顺序执行特定指令操作但不依赖于特定指令操作的指令操作不重新发行。 相应地，可以通过清除特定指令和所有更年轻的指令操作并重新获取特定的指令操作来进一步减少非推测性地执行不正确地调度指令操作的惩罚。

公开(公告)号：US06523109B1

公开(公告)日：2003-02-18

申请号：US09433189

申请日：1999-10-25

申请人： Stephan G. Meier

发明人： Stephan G. Meier

IPC分类号： G06F944

CPC分类号： G06F9/3826 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3861

摘要： A processor includes a store queue configured to detect a hit on a store queue entry for a load being executed by the processor, and to forward data from the store queue entry to provide a result for the load. The store queue data is provided to the data cache, along with an indication of how much data is being provided (e.g. byte enables). The data cache may then fill in any additional data accessed by the load from cache data, and provide a load result. Additionally, the store queue is configured to detect if more than one store queue entry is hit (i.e. that more than one store within the store queue updates at least one byte accessed by the load), referred to as a multimatch. If a multimatch is detected, the store queue retries the load. Subsequently, the load may be reexecuted and may not multimatch (as entries are deleted upon completion of the corresponding stores). The load may complete when it does not multimatch. In one embodiment, the store queue independently detects hits on the upper and lower portions of each store queue entry (e.g. doubleword portions) and forwards from the upper and lower portions independently. Thus, a load may hit one store queue entry for the lower portion of the data accessed by the load and a different store queue entry for the upper portion of the data accessed by the load without multimatch detection.

摘要翻译： 处理器包括存储队列，其被配置为检测由处理器执行的负载的存储队列条目的命中，以及从存储队列条目转发数据以提供负载的结果。 存储队列数据被提供给数据高速缓存，以及提供多少数据的指示（例如，字节使能）。 然后，数据高速缓存可以填充来自高速缓存数据的负载访问的任何附加数据，并提供负载结果。 此外，存储队列被配置为检测是否命中多于一个存储队列条目（即，存储队列内的多于一个存储器更新由负载访问的至少一个字节），被称为多映象。 如果检测到多重检测，则存储队列将重试加载。 随后，可以重新执行加载，并且可能不会进行多重映射（当对应的存储完成时，条目被删除）。 负载可能在不进行多重测量时完成。 在一个实施例中，存储队列独立地检测每个存储队列条目的上部和下部的命中（例如双字部分），并独立地从上部和下部前进。 因此，负载可以针对由负载访问的数据的较低部分命中一个存储队列条目，以及针对由负载访问的数据的上部的不同的存储队列条目，而不进行多重检测。

公开(公告)号：US06481251B1

公开(公告)日：2002-11-19

申请号：US09433184

申请日：1999-10-25

申请人： Stephan G. Meier ,  Ramsey W. Haddad

发明人： Stephan G. Meier ,  Ramsey W. Haddad

IPC分类号： G06F300

CPC分类号： G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  Y10T70/489

摘要： A processor includes a store queue and a store queue number assignment circuit. The store queue number assignment circuit assigns store queue numbers to stores, and operates upon instruction operations prior to the instruction operations reaching a point in the pipeline of the processor at which out of order instruction processing begins. Thus, store queue entries may be reserved for stores according to the program order of the stores. Additionally, in one embodiment, the store queue number identifying the youngest store represented in the store queue may be assigned to loads. In this manner, loads may determine which stores in the store queue are older or younger than the load based on relative position within the store queue. Checking for store queue hits may be qualified with the entries between the head of the store queue and the entry indicated by the load's store queue number. In one particular embodiment, the store queue number may include an additional “toggle” bit which is toggled each time the assignment of store queue numbers reaches the maximum store queue entry and wraps to zero. If the toggle bit of the store in the store queue entry identified by the load's store queue number differs from the toggle bit of the load's store queue number, than the store queue entry has been reassigned to a store younger than the load.

摘要翻译： 处理器包括存储队列和存储队列号分配电路。 存储队列号分配电路分配存储队列号以存储，并且在指令操作到达处理器的流水线之点的指令操作之前进行操作，在该处理器的流水线处，开始无序指令处理。 因此，存储队列条目可以根据商店的程序顺序保留用于商店。 另外，在一个实施例中，识别存储队列中表示的最小存储的存储队列号可被分配给负载。 以这种方式，负载可以基于存储队列内的相对位置来确定存储队列中的哪些存储器比负载更老或更小。 可以使用存储队列的头部和负载的存储队列号指示的条目之间的条目来限定检查存储队列命中。 在一个特定实施例中，存储队列号可以包括在每次存储队列号的分配达到最大存储队列条目并且转换为零时切换的附加“切换”位。 如果由加载存储队列号识别的存储队列条目中的存储的切换位与加载存储队列号的切换位不同，则存储队列条目已经重新分配给小于加载的存储。

公开(公告)号：US06405305B1

公开(公告)日：2002-06-11

申请号：US09394024

申请日：1999-09-10

申请人： Stephan G. Meier ,  Jeffrey E. Trull ,  Derrick R. Meyer ,  Norbert Juffa

发明人： Stephan G. Meier ,  Jeffrey E. Trull ,  Derrick R. Meyer ,  Norbert Juffa

IPC分类号： G06F9302

CPC分类号： G06F9/30087 ,  G06F9/30043 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861

摘要： A microprocessor with a floating point unit configured to rapidly execute floating point load control word (FLDCW) type instructions in an out of program order context is disclosed. The floating point unit is configured to schedule instructions older than the FLDCW-type instruction before the FLDCW-type instruction is scheduled. The FLDCW-type instruction acts as a barrier to prevent instructions occurring after the FLDCW-type instruction in program order from executing before the FLDCW-type instruction. Indicator bits may be used to simplify instruction scheduling, and copies of the floating point control word may be stored for instruction that have long execution cycles. A method and computer configured to rapidly execute FLDCW-type instructions in an out of program order context are also disclosed.

摘要翻译： 具有浮点单元的微处理器被配置为在程序顺序上下文中快速执行浮点负载控制字（FLDCW）类型指令。 浮点单元被配置为在调度FLDCW类型指令之前调度比FLDCW类型指令更早的指令。 FLDCW型指令作为屏障，以防止在FLDCW类型指令之前执行FLDCW类型指令之后的程序顺序发生的指令。 指示符位可以用于简化指令调度，并且可以存储具有长执行周期的指令的浮点控制字的副本。 还公开了一种配置成在程序顺序上下文中快速执行FLDCW型指令的方法和计算机。

公开(公告)号：US6076151A

公开(公告)日：2000-06-13

申请号：US948947

申请日：1997-10-10

申请人： Stephan G. Meier

发明人： Stephan G. Meier

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F17/30

CPC分类号： G06F12/0875 ,  G06F9/3455 ,  G06F9/383 ,  Y10S707/99953 ,  Y10S707/99956

摘要： A dynamic memory allocation routine maintains an allocation size cache which records the address of a most recently allocated memory block for each different size of memory block that has been allocated. Upon receiving a dynamic memory allocation request, the dynamic memory allocation routine determines if the requested size is equal to one of the sizes recorded in the allocation size cache. If a matching size is found, the dynamic memory allocation routine attempts to allocate a memory block contiguous to the most recently allocated memory block of that matching size. If the contiguous memory block has been allocated to another memory block, the dynamic memory allocation routine attempts to reserve a reserved memory block having a size which is a predetermined multiple of the requested size. The requested memory block is then allocated at the beginning of the reserved memory block. By reserving the reserved memory block, the dynamic memory allocation routine may increase the likelihood that subsequent requests for memory blocks having the requested size can be allocated in contiguous memory locations.

摘要翻译： 动态存储器分配程序维护分配大小高速缓存，其记录已分配的每个不同大小的存储器块的最近分配的存储块的地址。 在接收到动态存储器分配请求时，动态存储器分配例程确定所请求的大小是否等于记录在分配大小高速缓存中的尺寸之一。 如果找到匹配的大小，则动态内存分配例程尝试分配与该匹配大小最近分配的内存块相邻的内存块。 如果连续存储器块已被分配给另一个存储器块，则动态存储器分配例程尝试预留具有所请求大小的预定倍数的大小的保留存储器块。 然后，请求的存储器块在保留的存储器块的开头被分配。 通过保留保留的存储器块，动态存储器分配程序可以增加对具有所请求大小的存储器块的后续请求可以在连续存储器位置中分配的可能性。

公开(公告)号：US06442677B1

公开(公告)日：2002-08-27

申请号：US09329497

申请日：1999-06-10

申请人： Derrick R. Meyer ,  Stephan G. Meier ,  Norbert Juffa

发明人： Derrick R. Meyer ,  Stephan G. Meier ,  Norbert Juffa

IPC分类号： G06F9312

CPC分类号： G06F9/30043 ,  G06F9/3826

摘要： An apparatus and method for superforwarding load operands in a microprocessor are provided. An execution unit in a microprocessor is configured to receive a load instruction and a subsequent instruction. If the load instruction corresponds to a simple load instruction, a destination operand of the load instruction can be superforwarded to a subsequent instruction if the subsequent instruction specifies a source operand that depends on the destination operand of the load instruction. The subsequent instruction is not required to wait until a load instruction executes or completes and can be scheduled and/or executed prior to or at the same time as the load instruction. Consequently, latencies associated with operand dependencies may be reduced.

摘要翻译： 提供了一种用于在微处理器中超载负载操作数的装置和方法。 微处理器中的执行单元被配置为接收加载指令和后续指令。 如果加载指令对应于简单的加载指令，则如果后续指令指定依赖于加载指令的目的地操作数的源操作数，则加载指令的目标操作数可以被超前给后续指令。 后续指令不需要等待加载指令执行或完成，并且可以在加载指令之前或同时进行调度和/或执行。 因此，可以减少与操作数相关性相关联的延迟。

公开(公告)号：US06425074B1

公开(公告)日：2002-07-23

申请号：US09393524

申请日：1999-09-10

申请人： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

发明人： Stephan G. Meier ,  Norbert Juffa ,  Frederick D. Weber ,  Stuart F. Oberman

IPC分类号： G06F9302

CPC分类号： G06F9/30021 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859

摘要： A microprocessor configured to rapidly execute floating point store status word (FSTSW) type instructions that are immediately preceded by floating point compare (FCOM) type instructions is disclosed. FCOM-type instructions are modified to store their results to an architectural floating point status word and a temporary destination register. If an FSTSW-type instruction is detected immediately following an FCOM-type instruction, then the FSTSW-type instruction is transformed into a special fast floating point store status word (FSTSWEF) instruction. Unlike the FSTSW-type instruction, which is serializing and negatively impacts performance, the FSTSWEF instruction is not serializing and allows execution to continue without undue serialization. A computer system and method for rapidly executing FSTSW instructions immediately preceded by FCOM-type instructions are also disclosed.

摘要翻译： 公开了一种被配置为快速执行浮点比较（FCOM）类型指令之前的浮点存储状态字（FSTSW）类型指令的微处理器。 修改FCOM类型的指令以将其结果存储到架构浮点状态字和临时目标寄存器。 如果在FCOM型指令之后立即检测到FSTSW型指令，则FSTSW型指令被转换为特殊的快速浮点存储状态字（FSTSWEF）指令。 与串行化和负面影响性能的FSTSW型指令不同，FSTSWEF指令不是序列化的，允许执行继续，而不会过多的序列化。 还公开了一种用于在紧接在FCOM型指令之前快速执行FSTSW指令的计算机系统和方法。