公开(公告)号：US06941406B2

公开(公告)日：2005-09-06

申请号：US10861624

申请日：2004-06-04

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

公开(公告)号：US07596148B2

公开(公告)日：2009-09-29

申请号：US11786275

申请日：2007-04-11

申请人： Manu Gulati ,  Laurent R. Moll ,  James B. Keller

发明人： Manu Gulati ,  Laurent R. Moll ,  James B. Keller

IPC分类号： H04L12/28

CPC分类号： G06F13/4247

摘要： A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

摘要翻译： 用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段，其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段，并且其中数据段 所述多个数据段对应于所述多路复用数据片段中的一个。 该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。 该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。 该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

公开(公告)号：US06748479B2

公开(公告)日：2004-06-08

申请号：US10270029

申请日：2002-10-11

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F1300

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US07551645B2

公开(公告)日：2009-06-23

申请号：US10685231

申请日：2003-10-14

申请人： Manu Gulati ,  Laurent R. Moll

发明人： Manu Gulati ,  Laurent R. Moll

IPC分类号： H04J3/24

CPC分类号： H04L49/552 ,  H04L49/3072

摘要： A re-assembly buffer for use in interim storage of aligned data and to reassemble data output onto a wider internal data path, in which the width of the data path is determined to have sufficient bandwidth to account for frequency scaling of received data rate to frequency of the data path and fragmentation of data for alignment onto the data path. The buffer may be is arranged into arrays using single read port, single write port memory devices.

摘要翻译： 一种重组缓冲器，用于对准数据的临时存储并将数据输出重新组合到更宽的内部数据路径上，其中数据路径的宽度被确定为具有足够的带宽以将接收到的数据速率频率缩放到频率 的数据路径和数据碎片，以便对准数据路径。 可以使用单个读取端口，单个写入端口存储器件将缓冲器布置成阵列。

公开(公告)号：US08176229B2

公开(公告)日：2012-05-08

申请号：US12362679

申请日：2009-01-30

申请人： Laurent R. Moll ,  Manu Gulati

发明人： Laurent R. Moll ,  Manu Gulati

IPC分类号： G06F13/20

CPC分类号： G06F13/423

摘要： A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter-data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module can be configured in a first mode when supporting an aspect of the HyperTransport Standard and configured in a second mode when supporting the at least one other interface standard. In the alternative, a plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner.

摘要翻译： 双模式数字接口支持超传输标准和至少一种其他接口标准。 双模数字接口包括多个数据线去歪斜/采样块，数据组歪斜模块和启用控制模块。 多个数据线去歪斜/采样块基于时钟信号在相应数据线上进行去歪斜和采样输入数据以产生偏斜数据。 数据组去偏移模块从多个数据线去歪斜/采样块中的每一个接收偏斜数据，并从数据交换数据中去除数据间偏移，产生接收到的数据。 当支持超传输标准的一个方面并且在支持至少一个其他接口标准时以第二模式配置时，多个数据线去歪斜/采样块和数据组歪斜模块可被配置为第一模式。 在替代方案中，可以基于从链路伙伴接收到的训练序列来设置多个数据线去歪斜/采样块和数据组歪斜模块。

公开(公告)号：US07680140B2

公开(公告)日：2010-03-16

申请号：US11803637

申请日：2007-05-15

申请人： Barton Sano ,  Laurent R. Moll ,  Manu Gulati

发明人： Barton Sano ,  Laurent R. Moll ,  Manu Gulati

IPC分类号： H04L12/56

CPC分类号： H04L47/40

摘要： An integrated circuit includes receive circuits for receiving packets, transmit circuits for transmitting packets, a packet DMA circuit for communicating packets to and from a memory controller, and a switch for selectively coupling the receive circuits to transmit circuits. The integrated circuit may flexibly merge and split the packet streams to provide for various packet processing/packet routing functions to be applied to different packets within the packet streams. An apparatus may include two or more of the integrated circuits, which may communicate packets between respective receive and transmit circuits.

摘要翻译： 集成电路包括用于接收分组的接收电路，用于发送分组的发送电路，用于向存储器控制器传送分组的分组DMA电路和用于选择性地将接收电路耦合到发送电路的开关。 集成电路可以灵活地合并和拆分分组流，以提供要应用于分组流内的不同分组的各种分组处理/分组路由功能。 装置可以包括两个或更多个集成电路，其可以在相应的接收和发送电路之间传送分组。

公开(公告)号：US20090138749A1

公开(公告)日：2009-05-28

申请号：US12362679

申请日：2009-01-30

申请人： Laurent R. Moll ,  Manu Gulati

发明人： Laurent R. Moll ,  Manu Gulati

IPC分类号： G06F11/00

CPC分类号： G06F13/423

摘要： A dual mode digital interface supports the HyperTransport Standard and at least one other interface standard. The dual mode digital interface includes a plurality of data line deskew/sampling blocks, a data group deskew module, and an enablement control module. The plurality of data line deskew/sampling blocks deskew and sample incoming data on respective data lines based upon a clock signal to produce deskewed data. The data group deskew module receives deskewed data from each of the plurality of data line deskew/sampling blocks and removes inter-data line skew from the deskewed data to produce received data. The plurality of data line deskew/sampling blocks and the data group deskew module can be configured in a first mode when supporting an aspect of the HyperTransport Standard and configured in a second mode when supporting the at least one other interface standard. In the alternative, a plurality of data line deskew/sampling blocks and the data group deskew module may be set based upon a training sequence received from a link partner.

摘要翻译： 双模式数字接口支持超传输标准和至少一种其他接口标准。 双模数字接口包括多个数据线去歪斜/采样块，数据组歪斜模块和启用控制模块。 多个数据线去歪斜/采样块基于时钟信号在相应数据线上进行去歪斜和采样输入数据以产生偏斜数据。 数据组去偏移模块从多个数据线去歪斜/采样块中的每一个接收偏斜数据，并从数据交换数据中去除数据间偏移，产生接收到的数据。 当支持超传输标准的一个方面并且在支持至少一个其他接口标准时以第二模式配置时，多个数据线去歪斜/采样块和数据组歪斜模块可被配置为第一模式。 在替代方案中，可以基于从链路伙伴接收到的训练序列来设置多个数据线去歪斜/采样块和数据组歪斜模块。

公开(公告)号：US06912602B2

公开(公告)日：2005-06-28

申请号：US10269666

申请日：2002-10-11

申请人： Barton J. Sano ,  Koray Oner ,  Laurent R. Moll ,  Manu Gulati

发明人： Barton J. Sano ,  Koray Oner ,  Laurent R. Moll ,  Manu Gulati

IPC分类号： G06F13/28 ,  H04L12/56

CPC分类号： H04L49/10 ,  H04L49/602

摘要： An apparatus includes a first interface circuit, a second interface circuit, a memory controller for configured to interface to a memory, and a packet DMA circuit. The first interface circuit is configured to couple to a first interface for receiving and transmitting packet data. Similarly, the second interface circuit is configured to couple to a second interface for receiving and transmitting packet data. The packet DMA circuit is coupled to receive a first packet from the first interface circuit and a second packet from the second interface circuit. The packet DMA circuit is configured to transmit the first packet and the second packet in write commands to the memory controller to be written to the memory. In some embodiments, a switch is coupled to the first interface circuit, the second interface circuit, and the packet DMA circuit.

摘要翻译： 一种装置包括第一接口电路，第二接口电路，用于配置为与存储器接口的存储器控​​制器和分组DMA电路。 第一接口电路被配置为耦合到用于接收和发送分组数据的第一接口。 类似地，第二接口电路被配置为耦合到用于接收和发送分组数据的第二接口。 分组DMA电路被耦合以从第一接口电路接收第一分组，并从第二接口电路接收第二分组。 分组DMA电路被配置为以写入命令将第一分组和第二分组发送到存储器控制器以写入存储器。 在一些实施例中，开关耦合到第一接口电路，第二接口电路和分组DMA电路。

公开(公告)号：US07424561B2

公开(公告)日：2008-09-09

申请号：US11717511

申请日：2007-03-13

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  Laurent R. Moll ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  Laurent R. Moll ,  Manu Gulati

IPC分类号： G06F13/42 ,  G06F13/14 ,  G06F13/36 ,  G06F12/00

CPC分类号： G06F13/4022

摘要： An apparatus may include a first system and a second system. The first system includes a first plurality of interface circuits, and each of the first plurality of interface circuits is configured to couple to a separate interface. The second system includes a second plurality of interface circuits, and each of the second plurality of interface circuits is configured to couple to a separate interface. A first interface circuit of the first plurality of interface circuits and a second interface circuit of the second plurality of interface circuits are coupled to a first interface. Both the first interface circuit and the second interface circuit are configured to communicate packets, coherency commands, and noncoherent commands on the first interface.

摘要翻译： 装置可以包括第一系统和第二系统。 第一系统包括第一多个接口电路，并且第一多个接口电路中的每一个配置成耦合到单独的接口。 第二系统包括第二多个接口电路，并且第二多个接口电路中的每一个被配置为耦合到单独的接口。 第一多个接口电路的第一接口电路和第二多个接口电路的第二接口电路耦合到第一接口。 第一接口电路和第二接口电路均被配置为在第一接口上传送分组，相关命令和非相干命令。

公开(公告)号：US07313146B2

公开(公告)日：2007-12-25

申请号：US10684989

申请日：2003-10-14

申请人： Laurent R. Moll ,  Manu Gulati ,  Joseph B. Rowlands

发明人： Laurent R. Moll ,  Manu Gulati ,  Joseph B. Rowlands

IPC分类号： H04L12/56

CPC分类号： G06F3/00 ,  H04J3/16 ,  H04J3/22 ,  H04L12/50 ,  H04L12/56

摘要： A system for servicing packet data transactions and input/output transactions includes an input port, an output port, a node controller, a packet manager, and a switching module. The input port is receives communications from a communicatively coupled processing device that include packet data transactions and input/output transactions. The output port transmits communications to a communicatively coupled processing device that include packet data transactions and input/output transactions. The node controller communicatively couples to a system bus of the processing device and services input/output transactions. The packet manager communicatively couples to the system bus of the processing device and services packet data transactions. A switching module communicatively couples to the input port, the output port, the node controller, and the packet manager and services the exchange of transaction cells among the input port, the output port, the node controller, and the packet manager. Each transaction cell has a control tag and data and carrying all or a portion of a packet data transaction or an input/output transaction.

摘要翻译： 用于对分组数据事务和输入/输出事务进行服务的系统包括输入端口，输出端口，节点控制器，分组管理器和交换模块。 输入端口从包括分组数据事务和输入/输出事务的通信耦合的处理设备接收通信。 输出端口将通信发送到包括分组数据事务和输入/输出事务的通信耦合处理设备。 节点控制器通信地耦合到处理设备的系统总线并且服务输入/输出事务。 分组管理器通信地耦合到处理设备的系统总线和服务分组数据事务。 交换模块通信地耦合到输入端口，输出端口，节点控制器和分组管理器，并且为输入端口，输出端口，节点控制器和分组管理器之间的事务单元的交换提供服务。 每个事务单元具有控制标签和数据，并且携带分组数据事务或输入/输出事务的全部或一部分。