Receiving data from virtual channels
    2.
    发明授权
    Receiving data from virtual channels 失效
    从虚拟通道接收数据

    公开(公告)号:US07596148B2

    公开(公告)日:2009-09-29

    申请号:US11786275

    申请日:2007-04-11

    IPC分类号: H04L12/28

    CPC分类号: G06F13/4247

    摘要: A method for receiving data from a plurality of virtual channels begins by storing a stream of data as a plurality of data segments, wherein the stream of data includes multiplexed data fragments from at least one of the plurality of virtual channels, and wherein a data segment of the plurality of data segments corresponds to one of the multiplexed data fragments. The method continues by decoding at least one of the plurality of data segments in accordance with one of a plurality of data transmission protocols to produce at least one decoded data segment. The method continues by storing the at least one decoded data segment, in a generic format, to reassemble at least a portion of a packet provided by the at least one of the plurality of virtual channels. The method continues by routing the at least one decoded data segment as at least part of the reassembled packet to one of a plurality of destinations in accordance with the at least one of the plurality of virtual channels.

    摘要翻译: 用于从多个虚拟频道接收数据的方法开始于将数据流存储为多个数据段,其中数据流包括来自多个虚拟通道中的至少一个的多路复用数据片段,并且其中数据段 所述多个数据段对应于所述多路复用数据片段中的一个。 该方法通过根据多个数据传输协议之一对多个数据段中的至少一个解码以产生至少一个解码的数据段来继续。 该方法通过以通用格式存储至少一个解码的数据段来重新组合由多个虚拟通道中的至少一个提供的分组的至少一部分来继续。 该方法通过根据多个虚拟信道中的至少一个将至少一个解码的数据段作为至少部分重新组装的分组路由到多个目的地之一来继续。

    System having interfaces and switch that separates coherent and packet traffic
    3.
    发明授权
    System having interfaces and switch that separates coherent and packet traffic 有权
    具有分离相干和分组业务的接口和交换机的系统

    公开(公告)号:US06748479B2

    公开(公告)日:2004-06-08

    申请号:US10270029

    申请日:2002-10-11

    IPC分类号: G06F1300

    摘要: An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

    摘要翻译: 一种装置包括一个或多个接口电路,互连,存储器控制器,存储器桥,分组DMA电路和开关。 存储器控制器,存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路,存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

    Bandwidth Management
    4.
    发明申请
    Bandwidth Management 有权
    带宽管理

    公开(公告)号:US20140086070A1

    公开(公告)日:2014-03-27

    申请号:US13625416

    申请日:2012-09-24

    IPC分类号: H04L12/26

    CPC分类号: G06F13/1605 Y02D10/14

    摘要: In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.

    摘要翻译: 在一些实施例中,系统包括共享的高带宽资源(例如,存储器系统),被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。 通信结构可以配备有限制器,其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。 例如,性能度量可以包括延迟,未决事务数量,资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。 在一个实施例中,系统可以包括用于性能度量的多个阈值,并且超过给定阈值可以包括修改通信结构中的限制器。 在一些实施例中,也可能在系统中实现滞后,以减少配置之间的转换频率。

    Bandwidth management
    5.
    发明授权
    Bandwidth management 有权
    带宽管理

    公开(公告)号:US08848577B2

    公开(公告)日:2014-09-30

    申请号:US13625416

    申请日:2012-09-24

    IPC分类号: H04L12/28

    CPC分类号: G06F13/1605 Y02D10/14

    摘要: In some embodiments, a system includes a shared, high bandwidth resource (e.g. a memory system), multiple agents configured to communicate with the shared resource, and a communication fabric coupling the multiple agents to the shared resource. The communication fabric may be equipped with limiters configured to limit bandwidth from the various agents based on one or more performance metrics measured with respect to the shared, high bandwidth resource. For example, the performance metrics may include one or more of latency, number of outstanding transactions, resource utilization, etc. The limiters may dynamically modify their limit configurations based on the performance metrics. In an embodiment, the system may include multiple thresholds for the performance metrics, and exceeding a given threshold may include modifying the limiters in the communication fabric. There may be hysteresis implemented in the system as well in some embodiments, to reduce the frequency of transitions between configurations.

    摘要翻译: 在一些实施例中,系统包括共享的高带宽资源(例如,存储器系统),被配置为与共享资源通信的多个代理以及将多个代理耦合到共享资源的通信结构。 通信结构可以配备有限制器,其被配置为基于针对共享的高带宽资源测量的一个或多个性能度量来限制来自各种代理的带宽。 例如,性能度量可以包括延迟,未决事务数量,资源利用等中的一个或多个。限制器可以基于性能度量动态修改其限制配置。 在一个实施例中,系统可以包括用于性能度量的多个阈值,并且超过给定阈值可以包括修改通信结构中的限制器。 在一些实施例中,也可能在系统中实现滞后,以减少配置之间的转换频率。

    Fabric limiter circuits
    6.
    发明授权
    Fabric limiter circuits 有权
    织物限制电路

    公开(公告)号:US08744602B2

    公开(公告)日:2014-06-03

    申请号:US13008171

    申请日:2011-01-18

    IPC分类号: G05B11/01 H04W4/00

    CPC分类号: H04L49/10

    摘要: One or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, for example. Some systems that include a hierarchical communication fabric may also include fabric control circuits that may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

    摘要翻译: 可以将一个或多个结构控制电路插入到通信结构中,以通过系统中的组件来控制通信的各个方面。 例如,结构控制电路可以包括在组件的接口到通信结构。 包括分级通信结构的一些系统还可以包括可以可选地或另外包括的结构控制电路。 织物控制电路可以是可编程的,因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

    REGISTER FILE POWER SAVINGS
    7.
    发明申请
    REGISTER FILE POWER SAVINGS 有权
    注册文件节电

    公开(公告)号:US20130290681A1

    公开(公告)日:2013-10-31

    申请号:US13460178

    申请日:2012-04-30

    IPC分类号: G06F9/30

    摘要: A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

    摘要翻译: 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令,每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分,可以忽略给定的数值。

    ZERO CYCLE MOVE
    9.
    发明申请

    公开(公告)号:US20130275720A1

    公开(公告)日:2013-10-17

    申请号:US13447651

    申请日:2012-04-16

    IPC分类号: G06F9/30 G06F9/312

    CPC分类号: G06F9/30032 G06F9/384

    摘要: A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

    摘要翻译: 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样,则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外,寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

    Fabric Limiter Circuits
    10.
    发明申请
    Fabric Limiter Circuits 有权
    织物限制器电路

    公开(公告)号:US20120185062A1

    公开(公告)日:2012-07-19

    申请号:US13008171

    申请日:2011-01-18

    IPC分类号: G05B15/00

    CPC分类号: H04L49/10

    摘要: In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

    摘要翻译: 在一个实施例中,可以将一个或多个结构控制电路插入到通信结构中,以通过系统中的组件来控制通信的各个方面。 在一些实施例中,结构控制电路可以包括在组件的接口上到通信结构。 在包括分层通信结构的其他实施例中,结构控制电路可以可选地或另外包括。 织物控制电路可以是可编程的,因此可以提供调谐通信结构以满足性能和/或功能目标的能力。