公开(公告)号：US07228386B2

公开(公告)日：2007-06-05

申请号：US10950275

申请日：2004-09-24

申请人： Joseph B. Rowlands ,  James B. Keller

发明人： Joseph B. Rowlands ,  James B. Keller

IPC分类号： G06F12/00

CPC分类号： G06F12/0802 ,  G06F12/126 ,  G06F2212/2515

摘要： A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

摘要翻译： 缓存可以被编程为禁用用于存储存储器数据（例如，响应于错过高速缓存的存储器事务）的分配中的一个或多个条目。 此外，高速缓存可以被编程为选择高速缓存的哪些条目被禁止分配。 由于禁用的条目未被分配以存储存储器数据，所以存储在高速缓存被编程为禁用条目的条目中的数据可以保留在高速缓存中。 在一个具体实现中，高速缓存还提供对直接访问事务的响应的直接访问。

公开(公告)号：US06848024B1

公开(公告)日：2005-01-25

申请号：US09633683

申请日：2000-08-07

申请人： Joseph B. Rowlands ,  James B. Keller

发明人： Joseph B. Rowlands ,  James B. Keller

IPC分类号： G06F12/12 ,  G06F12/00

CPC分类号： G06F12/0802 ,  G06F12/126 ,  G06F2212/2515

摘要： A cache may be programmed to disable one or more entries from allocation for storing memory data (e.g. in response to a memory transaction which misses the cache). Furthermore, the cache may be programmed to select which entries of the cache are disabled from allocation. Since the disabled entries are not allocated to store memory data, the data stored in the entries at the time the cache is programmed to disable the entries may remain in the cache. In one specific implementation, the cache also provides for direct access to entries in response to direct access transactions.

公开(公告)号：US06965973B2

公开(公告)日：2005-11-15

申请号：US10269827

申请日：2002-10-11

申请人： Joseph B. Rowlands ,  James B. Keller

发明人： Joseph B. Rowlands ,  James B. Keller

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0817 ,  Y10S707/99952

摘要： A node is coupled to receive a coherency command and coupled to a memory, wherein the node includes a directory configured to track a state of a first number of coherency blocks less than a total number of the coherency blocks in the memory. The directory is configured to allocate a first entry to track the state of the first coherency block responsive to the coherency command. If the first entry is currently tracking the state of a second coherency block, the second node is configured to generate one or more coherency commands to invalidate the second coherency block in a plurality of nodes.

摘要翻译： 耦合节点以接收相关命令并耦合到存储器，其中节点包括被配置为跟踪小于存储器中的一致性块的总数的第一数量的一致性块的状态的目录。 该目录被配置为响应于一致性命令来分配第一条目以跟踪第一一致性块的状态。 如果第一条目当前正在跟踪第二相关块的状态，则第二节点被配置为生成一个或多个相关命令以使多个节点中的第二一致性块无效。

公开(公告)号：US06748479B2

公开(公告)日：2004-06-08

申请号：US10270029

申请日：2002-10-11

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F1300

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

摘要翻译： 一种装置包括一个或多个接口电路，互连，存储器控制器，存储器桥，分组DMA电路和开关。 存储器控制器，存储器桥和分组DMA电路耦合到互连。 每个接口电路耦合到相应的接口以从接口接收分组和/或一致性命令。 该开关耦合到接口电路，存储器桥和分组DMA电路。 交换机被配置为将来自接口电路的相干命令路由到存储器桥以及从接口电路到分组DMA电路的分组。 存储器桥被配置为响应于至少一些相关命令来在互连上发起相应的事务。 分组DMA电路被配置为将互连上的写入事务传送到存储器控制器以将数据包存储在存储器中。

公开(公告)号：US06941406B2

公开(公告)日：2005-09-06

申请号：US10861624

申请日：2004-06-04

申请人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

发明人： Barton J. Sano ,  Joseph B. Rowlands ,  James B. Keller ,  Laurent R. Moll ,  Koray Oner ,  Manu Gulati

IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F13/14 ,  G06F13/28 ,  G06F13/36 ,  G06F15/167 ,  H04L12/56 ,  H04Q11/00

CPC分类号： H04L49/901 ,  G06F12/0813 ,  G06F13/28 ,  H04L49/103 ,  H04L49/3009 ,  H04L49/90 ,  H04L49/9063 ,  H04L49/9073

摘要： An apparatus includes one or more interface circuits, an interconnect, a memory controller, a memory bridge, a packet DMA circuit, and a switch. The memory controller, the memory bridge, and the packet DMA circuit are coupled to the interconnect. Each interface circuit is coupled to a respective interface to receive packets and/or coherency commands from the interface. The switch is coupled to the interface circuits, the memory bridge, and the packet DMA circuit. The switch is configured to route the coherency commands from the interface circuits to the memory bridge and the packets from the interface circuits to the packet DMA circuit. The memory bridge is configured to initiate corresponding transactions on the interconnect in response to at least some of the coherency commands. The packet DMA circuit is configured to transmit write transactions on the interconnect to the memory controller to store the packets in memory.

公开(公告)号：US08744602B2

公开(公告)日：2014-06-03

申请号：US13008171

申请日：2011-01-18

申请人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

发明人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

IPC分类号： G05B11/01 ,  H04W4/00

CPC分类号： H04L49/10

摘要： One or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, for example. Some systems that include a hierarchical communication fabric may also include fabric control circuits that may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

摘要翻译： 可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。 例如，结构控制电路可以包括在组件的接口到通信结构。 包括分级通信结构的一些系统还可以包括可以可选地或另外包括的结构控制电路。 织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。

公开(公告)号：US20130290681A1

公开(公告)日：2013-10-31

申请号：US13460178

申请日：2012-04-30

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Sandeep Gupta

IPC分类号： G06F9/30

CPC分类号： G06F9/30141 ,  G06F1/3234 ,  G06F9/30112 ,  G06F9/384

摘要： A system and method for efficiently reducing the power consumption of register file accesses. A processor is operable to execute instructions with two or more data types, each with an associated size and alignment. Data operands for a first data type use operand sizes equal to an entire width of a physical register within a physical register file. Data operands for a second data type use operand sizes less than an entire width of a physical register. Accesses of the physical register file for operands associated with a non-full-width data type do not access a full width of the physical registers. A given numerical value may be bypassed for the portion of the physical register that is not accessed.

摘要翻译： 一种有效降低寄存器文件访问功耗的系统和方法。 处理器可操作以执行具有两个或多个数据类型的指令，每个数据类型具有相关联的大小和对齐。 第一种数据类型的数据操作数使用等于物理寄存器文件中物理寄存器的整个宽度的操作数大小。 第二种数据类型的数据操作数使用小于物理寄存器整个宽度的操作数大小。 访问与非全宽数据类型相关的操作数的物理寄存器文件不能访问物理寄存器的全部宽度。 对于未访问的物理寄存器的部分，可以忽略给定的数值。

公开(公告)号：US08566526B2

公开(公告)日：2013-10-22

申请号：US13545526

申请日：2012-07-10

申请人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

发明人： James Wang ,  Zongjian Chen ,  James B. Keller ,  Timothy J. Millet

IPC分类号： G06F13/00

CPC分类号： G06F3/0631 ,  G06F3/0604 ,  G06F3/0638 ,  G06F3/0673 ,  G06F12/0802 ,  G06F12/0831 ,  G06F12/0848 ,  G06F12/0853 ,  G06F12/0864 ,  G06F12/0877 ,  G06F12/125 ,  G06F2212/1021 ,  G06F2212/2515 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/62 ,  Y02D10/13

摘要： In one embodiment, a memory that is delineated into transparent and non-transparent portions. The transparent portion may be controlled by a control unit coupled to the memory, along with a corresponding tag memory. The non-transparent portion may be software controlled by directly accessing the non-transparent portion via an input address. In an embodiment, the memory may include a decoder configured to decode the address and select a location in either the transparent or non-transparent portion. Each request may include a non-transparent attribute identifying the request as either transparent or non-transparent. In an embodiment, the size of the transparent portion may be programmable. Based on the non-transparent attribute indicating transparent, the decoder may selectively mask bits of the address based on the size to ensure that the decoder only selects a location in the transparent portion.

公开(公告)号：US20130275720A1

公开(公告)日：2013-10-17

申请号：US13447651

申请日：2012-04-16

申请人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

发明人： James B. Keller ,  John H. Mylius ,  Conrado Blasco-Allue ,  Gerard R. Williams, III ,  Suparn Vats

IPC分类号： G06F9/30 ,  G06F9/312

CPC分类号： G06F9/30032 ,  G06F9/384

摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.

摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。

公开(公告)号：US20120185062A1

公开(公告)日：2012-07-19

申请号：US13008171

申请日：2011-01-18

申请人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

发明人： Gurjeet S. Saund ,  James B. Keller ,  Michael Frank

IPC分类号： G05B15/00

CPC分类号： H04L49/10

摘要： In an embodiment, one or more fabric control circuits may be inserted in a communication fabric to control various aspects of the communications by components in the system. The fabric control circuits may be included on the interface of the components to the communication fabric, in some embodiments. In other embodiments that include a hierarchical communication fabric, fabric control circuits may alternatively or additionally be included. The fabric control circuits may be programmable, and thus may provide the ability to tune the communication fabric to meet performance and/or functionality goals.

摘要翻译： 在一个实施例中，可以将一个或多个结构控制电路插入到通信结构中，以通过系统中的组件来控制通信的各个方面。 在一些实施例中，结构控制电路可以包括在组件的接口上到通信结构。 在包括分层通信结构的其他实施例中，结构控制电路可以可选地或另外包括。 织物控制电路可以是可编程的，因此可以提供调谐通信结构以满足性能和/或功能目标的能力。