公开(公告)号：US06748442B1

公开(公告)日：2004-06-08

申请号：US09477125

申请日：2000-01-03

申请人： James B. Keller

发明人： James B. Keller

IPC分类号： G06F1516

CPC分类号： G06F13/4217

摘要： A computer system has a communication link that includes a control signal and data lines. A first control packet having a-plurality of bytes is transferred over the data lines from a first to a second node on the communication link. The control line is asserted to indicate transfer of a control packet. After transfer of the first control packet, a first portion of a multi-byte data packet associated with the first control packet is transferred with the control line deasserted. During transfer of the data packet the control line is asserted and transfer of the data packet is suspended. A second control packet is then transferred over the data lines. Subsequent to transferring the second control packet, the remainder of the data packet is transferred with the control line deasserted.

摘要翻译： 计算机系统具有包括控制信号和数据线的通信链路。 具有多个字节的第一控制分组通过数据线从通信链路上的第一节点传送到第二节点。 控制线被断言以指示控制分组的传送。 在传送第一控制分组之后，与控制线无关地传送与第一控制分组相关联的多字节数据分组的第一部分。 在传输数据包的过程中，控制线被断言，数据包的传输被暂停。 然后通过数据线传输第二个控制数据包。 在传送第二控制分组之后，数据分组的其余部分被控制线断言传送。

公开(公告)号：US06714994B1

公开(公告)日：2004-03-30

申请号：US09429118

申请日：1999-10-27

申请人： James B. Keller ,  Derrick R. Meyer

发明人： James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F300

CPC分类号： G06F13/1621 ,  G06F13/405 ,  G06F15/17381

摘要： A computer system is presented which implements a system and method for conveying packets between a coherent processing subsystem and a non-coherent input/output (I/O) subsystem. The processing subsystem includes a first processing node coupled to a second processing node via a coherent communication link. The first processing node includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. The I/O subsystem includes an I/O node coupled to the first processing node via a non-coherent communication link. The I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The coherent and non-coherent communication links are physically identical. For example, the coherent and non-coherent communication links may have the same electrical interface and the same signal definition. The host bridge translates non-coherent packets from the I/O node to coherent packets, and transmits the coherent packets to the second processing node. The host bridge also translates coherent packets from the second processing node to non-coherent packets, and transmits the non-coherent packets to the I/O node. The coherent and non-coherent packets have identically located command fields. The translating process includes copying the contents of the command field of one packet type to the command field of the other packet type.

摘要翻译： 提出了一种实现用于在相干处理子系统和非相干输入/输出（I / O）子系统之间传送分组的系统和方法的计算机系统。 处理子系统包括经由相干通信链路耦合到第二处理节点的第一处理节点。 第一处理节点包括主转换台，其转换在处理子系统和I / O子系统之间移动的分组。 I / O子系统包括经由非相干通信链路耦合到第一处理节点的I / O节点。 I / O节点可以体现一个或多个I / O功能（例如，调制解调器，声卡等）。 相干和非相干的通信链路在物理上是相同的。 例如，相干和非相干通信链路可以具有相同的电接口和相同的信号定义。 主机桥将非相干分组从I / O节点转换为相关分组，并将相干分组发送到第二处理节点。 主桥还将来自第二处理节点的相干分组转换为非相干分组，并将非相干分组发送到I / O节点。 相干和非相干数据包具有相同的命令字段。 翻译处理包括将一个分组类型的命令字段的内容复制到另一个分组类型的命令字段。

公开(公告)号：US06633936B1

公开(公告)日：2003-10-14

申请号：US09670362

申请日：2000-09-26

申请人： James B. Keller ,  Chun H. Ning ,  Kwong-Tak A. Chui ,  Mark D. Hayter

发明人： James B. Keller ,  Chun H. Ning ,  Kwong-Tak A. Chui ,  Mark D. Hayter

IPC分类号： G06F1300

CPC分类号： G06F13/161

摘要： An adaptive retry mechanism may record latencies of recent transactions (e.g. the first data transfer latency), and may select a retry latency from two or more retry latencies. The retry latency may be used for a transaction, and may specify a point in time during the transaction at which the transaction is retried if the first data transfer has not yet occurred. In one implementation, the set of retry latencies includes a minimum retry latency, a nominal retry latency, and a maximum retry latency. The nominal retry latency may be set slightly greater than the expected latency of transactions in the system. The minimum retry latency may be less than the nominal retry latency and the maximum retry latency may be greater than the nominal retry latency. If latencies greater than the nominal retry latency but less than the maximum retry latency are being experienced, the maximum retry latency may be selected. On the other hand, if latencies greater than the maximum retry latency are being experienced, the minimum retry latency may be selected.

摘要翻译： 自适应重试机制可以记录近期事务的延迟（例如，第一数据传输等待时间），并且可以从两个或更多个重试延迟中选择重试延迟。 重试延迟可以用于事务，并且可以在事务中指定在第一数据传送尚未发生的情况下重试事务的时间点。 在一个实现中，该重试延迟集合包括最小重试延迟，标称重试延迟和最大重试延迟。 标称重试延迟可以被设置为略大于系统中事务的预期等待时间。 最小重试延迟可能小于标称重试延迟，并且最大重试延迟可能大于标称重试延迟。 如果正在经历大于标称重试延迟但小于最大重试延迟的延迟，则可以选择最大重试延迟。 另一方面，如果正在经历大于最大重试延迟的延迟，则可以选择最小重试延迟。

公开(公告)号：US06631401B1

公开(公告)日：2003-10-07

申请号：US09217367

申请日：1998-12-21

申请人： James B. Keller ,  Dale E. Gulick

发明人： James B. Keller ,  Dale E. Gulick

IPC分类号： G06F15167

CPC分类号： G06F12/0815 ,  G06F12/0817

摘要： A computer system may include multiple processing nodes, one or more of which may be coupled to separate memories which may form a distributed memory system. The processing nodes may include caches, and the computer system may maintain coherency between the caches and the distributed memory system. Particularly, the computer system may implement a flexible probe command/response routing scheme. The scheme may employ an indication within the probe command which identifies a receiving node to receive the probe responses. For example, probe commands indicating that the target or the source of transaction should receive probe responses corresponding to the transaction may be included. Probe commands may specify the source of the transaction as the receiving node for read transactions (such that dirty data is delivered to the source node from the node storing the dirty data). On the other hand, for write transactions (in which data is being updated in memory at the target node of the transaction), the probe commands may specify the target of the transaction as the receiving node. In this manner, the target may determine when to commit the write data to memory and may receive any dirty data to be merged with the write data.

摘要翻译： 计算机系统可以包括多个处理节点，其中的一个或多个处理节点可以耦合到可以形成分布式存储器系统的分离的存储器。 处理节点可以包括高速缓存，并且计算机系统可以保持高速缓存和分布式存储器系统之间的一致性。 特别地，计算机系统可以实现灵活的探测命令/响应路由方案。 该方案可以采用探测命令中的指示，该指示标识接收节点以接收探测响应。 例如，可以包括指示目标或事务源应该接收对应于事务的探测响应的探测命令。 探测命令可以将事务的来源指定为读取事务的接收节点（使得脏数据从存储脏数据的节点传送到源节点）。 另一方面，对于写入事务（其中数据正在事务的目标节点的存储器中更新），探测命令可以将事务的目标指定为接收节点。 以这种方式，目标可以确定何时将写入数据提交到存储器，并且可以接收要与写入数据合并的任何脏数据。

公开(公告)号：US06490661B1

公开(公告)日：2002-12-03

申请号：US09217212

申请日：1998-12-21

申请人： James B. Keller ,  Derrick R. Meyer

发明人： James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F1314

CPC分类号： G06F12/0813

摘要： A messaging scheme that accomplishes cache-coherent data transfers during a memory read operation in a multiprocessing computer system is described. A source processing node sends a read command to a target processing node to read data from a designated memory location in a system memory associated with the target processing node. In response to the read command, the target processing node transmits a probe command to all the remaining processing nodes in the computer system regardless of whether one or more of the remaining nodes have a copy of the data cached in their respective cache memories. Probe command causes each node to maintain cache coherency by appropriately changing the state of the cache block containing the requested data and by causing the node having an updated copy of the cache block to send the cache block to the source node. Each processing node that receives a probe command sends, in return, a probe response indicating whether that processing node has a cached copy of the data and the state of the cached copy if the responding node has the cached copy. The target node sends a read response including the requested data to the source node. The source node waits for responses from the target node and from each of the remaining node in the system and acknowledges the receipt of requested data by sending a source done response to the target node.

摘要翻译： 描述了在多处理计算机系统中的存储器读取操作期间实现高速缓存相干数据传输的消息传递方案。 源处理节点向目标处理节点发送读命令，以从与目标处理节点相关联的系统存储器中的指定存储器位置读取数据。 响应于读取命令，目标处理节点向计算机系统中的所有其余处理节点发送探测命令，而不管剩余节点中的一个或多个是否具有高速缓存在其各自高速缓冲存储器中的数据的副本。 Probe命令通过适当地改变包含所请求数据的缓存块的状态，并使得具有高速缓存块的更新副本的节点将高速缓存块发送到源节点，导致每个节点维持高速缓存一致性。 接收探测命令的每个处理节点作为回报发送指示该处理节点是否具有数据的缓存副本的探测响应以及响应节点是否具有缓存副本的缓存副本的状态。 目标节点将包含请求的数据的读取响应发送到源节点。 源节点等待来自目标节点和系统中的每个剩余节点的响应，并通过向目标节点发送源完成响应来确认所请求数据的接收。

公开(公告)号：US06473849B1

公开(公告)日：2002-10-29

申请号：US09398955

申请日：1999-09-17

申请人： James B. Keller ,  William A. Hughes

发明人： James B. Keller ,  William A. Hughes

IPC分类号： G06F1517

CPC分类号： G06F13/1657 ,  G06F13/4273

摘要： A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. The microcode within the lock requesting node transmits a write command to write corresponding node identification data into a lock register in the arbitrating node. The lock requesting node iteratively reads the lock register until it finds its node identification data stored therein with a valid bit set. The lock requesting node then informs all remaining processing nodes to release shared system resources. This is accomplished through a release request bit and a release response bit in each processing node. After completion of lock operations, the lock requesting node sends a message to the arbitrating node to reset the valid bit in the lock register, and a broadcast message to each remaining node to reset the release request bit. In an alternate embodiment, each processing node includes a lock resource register instead of a release response bit. Each remaining processing node writes its node identification data into the lock resource register within the lock requesting processing node when ready to release shared system resources to allow the lock requesting node to establish lock ownership. This informs the lock requesting node to commence lock operations. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.

摘要翻译： 用于使具有使用双向单向链路的互连结构互连的两个或多个处理节点的分布式存储器多处理计算机系统内的进程同步的消息传递方案。 锁请求节点内的微码发送写入命令，将相应的节点识别数据写入仲裁节点中的锁定寄存器。 锁请求节点迭代地读取锁定寄存器，直到找到其中存储有有效位的节点标识数据。 锁请求节点然后通知所有剩余的处理节点释放共享系统资源。 这通过每个处理节点中的释放请求位和释放响应位来实现。 在锁定操作完成之后，锁定请求节点向仲裁节点发送消息以重置锁定寄存器中的有效位，并向每个剩余节点发送广播消息以重置释放请求位。 在替代实施例中，每个处理节点包括锁定资源寄存器而不是释放响应位。 当准备释放共享系统资源以允许锁请求节点建立锁所有权时，每个剩余的处理节点将其节点标识数据写入锁请求处理节点内的锁资源寄存器。 这通知锁请求节点开始锁定操作。 执行锁定操作而不对系统资源产生争用，并且在各种处理节点之间没有死锁。

公开(公告)号：US06393546B1

公开(公告)日：2002-05-21

申请号：US09788067

申请日：2001-02-16

申请人： David B. Witt ,  James B. Keller

发明人： David B. Witt ,  James B. Keller

IPC分类号： G06F1202

CPC分类号： G06F9/384 ,  G06F9/3013 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857

摘要： A register renaming apparatus includes one or more physical registers which may be assigned to store a floating point value, a multimedia value, an integer value and corresponding condition codes, or condition codes only. The classification of the instruction (e.g. floating point, multimedia, integer, flags-only) defines which lookahead register state is updated (e.g. floating point, integer, flags, etc.), but the physical register can be selected from the one or more physical registers for any of the instruction types. Determining if enough physical registers are free for assignment to the instructions being selected for dispatch includes considering the number of instructions selected for dispatch and the number of free physical registers, but excludes the data type of the instruction. When a code sequence includes predominately instructions of a particular data type, many of the physical registers may be assigned to that data type (efficiently using the physical register resource). By contrast, if different sets of physical registers are provided for different data types, only the physical registers used for the particular data type may be used for the aforementioned code sequence. Additional efficiencies may be realized in embodiments in which an integer register and condition codes are both updated by many instructions. One physical register may concurrently represent the architected state of both the flags register and the integer register. Accordingly, a given functional unit may forward a single physical register number for both results.

摘要翻译： 寄存器重命名装置包括一个或多个物理寄存器，其可被分配用于仅存储浮点值，多媒体值，整数值和相应的条件代码或条件代码。 指令的分类（例如浮点，多媒体，整数，仅标志）定义哪个前瞻寄存器状态被更新（例如浮点，整数，标志等），但物理寄存器可以从一个或多个 任何指令类型的物理寄存器。 确定是否有足够的物理寄存器用于分配给选择用于调度的指令，包括考虑选择用于调度的指令数量和空闲物理寄存器的数量，但不包括指令的数据类型。 当代码序列主要包括特定数据类型的指令时，许多物理寄存器可被分配给该数据类型（有效地使用物理寄存器资源）。 相比之下，如果针对不同的数据类型提供不同的物理寄存器集合，则只有用于特定数据类型的物理寄存器可以用于上述代码序列。 在其中整数寄存器和条件码都被许多指令更新的实施例中可以实现额外的效率。 一个物理寄存器可以同时表示标志寄存器和整数寄存器的架构状态。 因此，给定的功能单元可以转发两个结果的单个物理寄存器号。

公开(公告)号：US06253301B1

公开(公告)日：2001-06-26

申请号：US09061626

申请日：1998-04-16

申请人： Rahul Razdan ,  David A. Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

发明人： Rahul Razdan ,  David A. Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F1215

CPC分类号： G06F12/1054 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/655

摘要： A data caching system and method includes a data store for caching data from a main memory, a primary tag array for holding tags associated with data cached in the data store, and a duplicate tag array which holds copies of the tags held in the primary tag array. The duplicate tag array is accessible by functions, such as external memory cache probes, such that the primary tag remains available to the processor core. An address translator maps virtual page addresses to physical page address. In order to allow a data caching system which is larger than a page size, a portion of the virtual page address is used to index the tag arrays and data store. However, because of the virtual to physical mapping, the data may reside in any of a number of physical locations. During an internally-generated memory access, the virtual address is used to look up the cache. If there is a miss, other combinations of values are substituted for the virtual bits of the tag array index. For external probes which provide physical addresses to the duplicate tag array, combinations of values are appended to the index portion of the physical address. Tag array lookups can be performed either sequentially, or in parallel.

摘要翻译： 数据缓存系统和方法包括用于缓存来自主存储器的数据的数据存储器，用于保存与缓存在数据存储器中的数据相关联的标签的主标签阵列，以及保存在主标签中的标签副本的重复标签阵列 数组。 重复的标签阵列可以通过诸如外部存储器高速缓存探测器的功能访问，使得主标签对于处理器核心仍然可用。 地址转换器将虚拟页面地址映射到物理页面地址。 为了允许大于页面大小的数据缓存系统，虚拟页面地址的一部分用于对标签数组和数据存储进行索引。 然而，由于虚拟到物理映射，数据可能驻留在多个物理位置中的任何一个中。 在内部生成的内存访问期间，虚拟地址用于查找缓存。 如果存在缺失，则代替标签数组索引的虚拟位的值的其他组合。 对于为重复标签数组提供物理地址的外部探测器，值的组合将附加到物理地址的索引部分。 标签阵列查找可以顺序地或并行地执行。

公开(公告)号：US6163821A

公开(公告)日：2000-12-19

申请号：US215354

申请日：1998-12-18

申请人： James B. Keller ,  Richard E. Kessler ,  Stephen C. Root ,  Paul Geoffrey Lowney

发明人： James B. Keller ,  Richard E. Kessler ,  Stephen C. Root ,  Paul Geoffrey Lowney

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F13/20 ,  G06F13/16 ,  G06F13/362

CPC分类号： G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

摘要： A computer method and apparatus causes the load-store instruction grouping in a microprocessor instruction pipeline to be disrupted at appropriate times. The computer method and apparatus employs a memory access member which periodically stalls the issuance of store instructions when there are prior store instructions pending in the store queue. The periodic stalls bias the issue stage to issue load groups and store instruction groups. In the latter case, the store queue is free to update the data cache with the data from previous store instructions. Thus, the invention memory access member biases issuance of store instructions in a manner that prevents the store queue from becoming full, and as such enables the store queue to write to the data cache before the store queue becomes full.

摘要翻译： 计算机方法和装置使得微处理器指令流水线中的加载存储指令分组在适当的时间被中断。 计算机方法和装置采用存储器访问部件，当在存储队列中存在先前的存储指令时，周期性地停止发布存储指令。 周期性档位偏离问题阶段以发布加载组并存储指令组。 在后一种情况下，存储队列可以使用来自先前存储指令的数据来自由地更新数据高速缓存。 因此，本发明的存储器访问部件以防止存储队列变满的方式偏移存储指令的发布，并且因此使存储队列在存储队列变满之前写入数据高速缓存。

公开(公告)号：US5202973A

公开(公告)日：1993-04-13

申请号：US546548

申请日：1990-06-29

申请人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

发明人： Raj Ramanujan ,  James B. Keller ,  Jay Stickney ,  Steven Ho ,  Paul Lemmon

IPC分类号： G06F13/16 ,  G06F13/376

CPC分类号： G06F13/161 ,  G06F13/376

摘要： A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controller and in view of the memory modules of the shared memory having different read access times, with the system and method being implemented in a system that includes a central unit and multiple uni-directional buses that are disposed between a shared memory and a plurality of processors, with the central unit controlling access to, and use of, the shared buses of the system.

摘要翻译： 用于控制多处理器系统的计算机中的共享存储器总线的系统和方法防止共享总线上的冲突，并确保总线在系统启动时已满。 维持稳定状态操作，而不需要系统存储器控制器中的排队机制，并且考虑到具有不同读取访问时间的共享存储器的存储器模块，系统和方法在包括中央单元和 多个单向总线设置在共享存储器和多个处理器之间，中央单元控制对系统的共享总线的访问和使用。