公开(公告)号：US06253301B1

公开(公告)日：2001-06-26

申请号：US09061626

申请日：1998-04-16

申请人： Rahul Razdan ,  David A. Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

发明人： Rahul Razdan ,  David A. Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F1215

CPC分类号： G06F12/1054 ,  G06F12/0864 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/655

摘要： A data caching system and method includes a data store for caching data from a main memory, a primary tag array for holding tags associated with data cached in the data store, and a duplicate tag array which holds copies of the tags held in the primary tag array. The duplicate tag array is accessible by functions, such as external memory cache probes, such that the primary tag remains available to the processor core. An address translator maps virtual page addresses to physical page address. In order to allow a data caching system which is larger than a page size, a portion of the virtual page address is used to index the tag arrays and data store. However, because of the virtual to physical mapping, the data may reside in any of a number of physical locations. During an internally-generated memory access, the virtual address is used to look up the cache. If there is a miss, other combinations of values are substituted for the virtual bits of the tag array index. For external probes which provide physical addresses to the duplicate tag array, combinations of values are appended to the index portion of the physical address. Tag array lookups can be performed either sequentially, or in parallel.

摘要翻译： 数据缓存系统和方法包括用于缓存来自主存储器的数据的数据存储器，用于保存与缓存在数据存储器中的数据相关联的标签的主标签阵列，以及保存在主标签中的标签副本的重复标签阵列 数组。 重复的标签阵列可以通过诸如外部存储器高速缓存探测器的功能访问，使得主标签对于处理器核心仍然可用。 地址转换器将虚拟页面地址映射到物理页面地址。 为了允许大于页面大小的数据缓存系统，虚拟页面地址的一部分用于对标签数组和数据存储进行索引。 然而，由于虚拟到物理映射，数据可能驻留在多个物理位置中的任何一个中。 在内部生成的内存访问期间，虚拟地址用于查找缓存。 如果存在缺失，则代替标签数组索引的虚拟位的值的其他组合。 对于为重复标签数组提供物理地址的外部探测器，值的组合将附加到物理地址的索引部分。 标签阵列查找可以顺序地或并行地执行。

公开(公告)号：US5142631A

公开(公告)日：1992-08-25

申请号：US306773

申请日：1989-02-03

申请人： John E. Murray ,  Mark A. Firstenberg ,  David B. Fite ,  Michael M. McKeon ,  Wiliam R. Grundmann ,  David A. Webb, Jr. ,  Ronald M. Salett ,  Tryggve Fossum ,  Dwight P. Manley ,  Ricky C. Hetherington

发明人： John E. Murray ,  Mark A. Firstenberg ,  David B. Fite ,  Michael M. McKeon ,  Wiliam R. Grundmann ,  David A. Webb, Jr. ,  Ronald M. Salett ,  Tryggve Fossum ,  Dwight P. Manley ,  Ricky C. Hetherington

IPC分类号： G06F9/38

CPC分类号： G06F9/355 ,  G06F9/345 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

公开(公告)号：US5019965A

公开(公告)日：1991-05-28

申请号：US306826

申请日：1989-02-03

申请人： David A. Webb, Jr. ,  Ricky C. Hetherington ,  Ronald M. Salett ,  Trvggve Fossum ,  Dwight P. Manley

发明人： David A. Webb, Jr. ,  Ricky C. Hetherington ,  Ronald M. Salett ,  Trvggve Fossum ,  Dwight P. Manley

IPC分类号： G06F12/08 ,  G06F13/40

CPC分类号： G06F12/0886 ,  G06F13/4018

摘要： In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

公开(公告)号：US4995041A

公开(公告)日：1991-02-19

申请号：US306703

申请日：1989-02-03

申请人： Ricky C. Hetherington ,  Tryggve Fossum ,  Maurice B. Steinman ,  David A. Webb, Jr.

发明人： Ricky C. Hetherington ,  Tryggve Fossum ,  Maurice B. Steinman ,  David A. Webb, Jr.

IPC分类号： G06F11/10 ,  G06F12/08 ,  G06F12/16

CPC分类号： G06F11/1048 ,  G06F11/1064 ,  G06F12/0804

摘要： In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses error correction code (ECC) hardware to ensure the integrity of the data delivered between the cache and main memory. The prevent the ECC hardware from slowing the overall operation of the CPU, the error correction is performed underneath a write back operation. Data contained in the cache, which will be displaced by data received from main memory 10, is transferred to a write back buffer (WBB) during that period of time between the request for data from the main memory and actual delivery of the requested data. Further, the ECC hardware also operates on the cache data being written to the WBB. Accordingly, a performance penalty is avoided by performing error correction and preremoving the cache data during that idle period of time.

公开(公告)号：US5349651A

公开(公告)日：1994-09-20

申请号：US746007

申请日：1991-08-09

申请人： Ricky C. Hetherington ,  David A. Webb, Jr. ,  David B. Fite ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

发明人： Ricky C. Hetherington ,  David A. Webb, Jr. ,  David B. Fite ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/00

CPC分类号： G06F12/0855 ,  G06F12/1045

摘要： In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addresses. With this arrangement the memory management unit can immediately access memory to retrieve the physical address upon a "miss" by the translation buffer cache.

摘要翻译： 在高速计算机领域，中央处理单元通常通过虚拟寻址方案而不是实际物理存储器地址来引用存储器位置。 在多任务环境中，这种虚拟寻址方案减少了访问相同物理内存位置的不同程序的可能性。 因此，为了维持计算机处理速度，使用高速转换缓冲器缓存来对存储器参考指令执行必要的虚拟到物理转换。 翻译缓冲区高速缓存存储多个先前转换的虚拟地址及其对应的物理地址。 使用存储器管理处理器来更新具有最近访问的物理存储器位置的翻译缓冲器高速缓存。 存储器管理处理器由控制硬件的状态机组成，其特别设计用于更新翻译缓冲器高速缓存。 存储器管理处理器计算存储器中与物理地址同时存储的位置的地址，该地址与翻译缓冲器高速缓存将虚拟地址与已存储的虚拟地址进行比较。 利用这种安排，存储器管理单元可以立即访问存储器，以在翻译缓冲器高速缓存器“遗漏”时检索物理地址。

公开(公告)号：US5222223A

公开(公告)日：1993-06-22

申请号：US306870

申请日：1989-02-03

申请人： David A. Webb, Jr. ,  Ricky C. Hetherington ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

发明人： David A. Webb, Jr. ,  Ricky C. Hetherington ,  John E. Murray ,  Tryggve Fossum ,  Dwight P. Manley

IPC分类号： G06F12/08 ,  G06F9/38 ,  G06F12/00 ,  G06F12/10 ,  G06F13/18

CPC分类号： G06F13/18 ,  G06F12/1054 ,  G06F9/3824

摘要： In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical address output from the translation buffer 30 are passed to a cache 28 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ, in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.

公开(公告)号：US4985825A

公开(公告)日：1991-01-15

申请号：US306866

申请日：1989-02-03

申请人： David A. Webb, Jr. ,  David B. Fite ,  Ricky C. Hetherington ,  Francis X. McKeen ,  Mark A. Firstenberg ,  John E. Murray ,  Dwight P. Manley ,  Ronald M. Salett ,  Tryggve Fossum

发明人： David A. Webb, Jr. ,  David B. Fite ,  Ricky C. Hetherington ,  Francis X. McKeen ,  Mark A. Firstenberg ,  John E. Murray ,  Dwight P. Manley ,  Ronald M. Salett ,  Tryggve Fossum

IPC分类号： G06F9/38 ,  G06F11/07 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F9/3865 ,  G06F11/073 ,  G06F11/0772 ,  G06F12/1045

摘要： A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.