-
91.
公开(公告)号:US20240134025A1
公开(公告)日:2024-04-25
申请号:US18491367
申请日:2023-10-19
Applicant: Arizona Board of Regents on Behalf of Arizona State University , Texas Instruments Incorporated
Inventor: Sule Ozev , Ferhat C. Ataman , Chethan Kumar Y.B. , Sandeep Rao
Abstract: A radar system applies various angle correction processes with varying levels of computational overhead to reduce errors in angle estimation when processing received return signals. The various angle correction processes aim to overcome systematic errors affected by range migration through correction based on simulation or hardware measurements, through non-iterative refinement, iterative refinement, and/or a combination of correction and iterative refinement.
-
公开(公告)号:US20240069186A1
公开(公告)日:2024-02-29
申请号:US18502445
申请日:2023-11-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Sandeep Rao , Karthik Subburaj
CPC classification number: G01S13/584 , G01S7/40
Abstract: A radar transceiver includes a phase shifter that is controlled to apply an induced phase shift in a first subset of chirp signals of a frame of chirp signals, which also includes a second subset of chirp signals in which no phase shift is applied. Other circuitry generates digital signals based on received reflected signals, which are based on transmitted signals. Processing circuitry performs a Fast Fourier Transform (FFT) on a first subset of digital signals, corresponding to the first subset of chirp signals, to generate a first range-Doppler array, and performs a FFT on the second subset of digital signals, corresponding to the second subset of chirp signals, to generate a second range-Doppler array; identifies peaks in the first and second range-Doppler arrays to detect an object; and compares a phases of peaks at corresponding positions in the first and second range-Doppler arrays to determine a measured phase shift between the two peaks.
-
公开(公告)号:US11846700B2
公开(公告)日:2023-12-19
申请号:US17132857
申请日:2020-12-23
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Sandeep Rao , Karthik Subburaj
CPC classification number: G01S13/584 , G01S7/40
Abstract: A radar system is provided and includes a radar transceiver integrated circuit (IC) and a processor coupled to the radar transceiver IC. The radar transceiver IC includes a chirp generator configured to generate a plurality of chirp signals and a phase shifter configured to induce a signal phase shift. The radar transceiver IC is configured to transmit a frame of chirps based on the plurality of chirp signals and generate a plurality of digital signals, each digital signal corresponding to a respective reflection received based on the plurality of chirp signals. The processor is configured to control the phase shifter to induce the signal phase shift in a first subset of chirp signals of the plurality of chirp signals and determine a phase shift induced in the first subset of chirp signals by the phase shifter based on the digital signal.
-
公开(公告)号:US11782148B2
公开(公告)日:2023-10-10
申请号:US16363719
申请日:2019-03-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Karthik Subburaj , Sandeep Rao , Sriram Murali , Karthik Ramasubramanian
CPC classification number: G01S13/584 , G01S7/352 , G01S7/356 , G01S13/343 , G01S13/345
Abstract: Aspects of the present disclosure provide for a radar system including a radar IC including a timing engine, a local oscillator, and a modulator. The timing engine is configured to generate one or more chirp control signals. The local oscillator is configured to receive the one or more chirp control signals and generate a frame including a first sequence of chirps according to the one or more chirp control signals. The modulator is configured to modulate the first sequence of chirps to generate a second sequence of chirps so the frame includes the first sequence of chirps and the second sequence of chirps offset by a first frequency value.
-
公开(公告)号:US20220308196A1
公开(公告)日:2022-09-29
申请号:US17388954
申请日:2021-07-29
Applicant: Texas Instruments Incorporated
Inventor: Sandeep Rao , Aleksandar Purkovic
Abstract: Methods and apparatus are disclosed low power motion detection by a radar apparatus. One example radar apparatus includes a transmitter to transmit a pattern of chirps. The transmitted pattern includes a first series of chirps transmitted during a first time period and a second series of chirps transmitted during a second time period that begins after passage of a sleep time period from an end of the first time period. The example radar apparatus also includes a receiver to detect returning chirps including reflected portions of the transmitted pattern. The example radar apparatus also includes analog to digital converter (ADC) coupled to the receiver. The ADC is to sample analog signals from the receiver to generate ADC samples for the returning chirps detected by the receiver.
-
公开(公告)号:US20220236399A1
公开(公告)日:2022-07-28
申请号:US17405303
申请日:2021-08-18
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Karthik Subburaj , Sandeep Rao
Abstract: A method for compressing echolocation data is provided. The method includes dividing the echolocation data into a plurality of partitions, and selecting a first partition for processing. The method also includes combining echolocation data from the first partition with echolocation data within a second partition, and combining echolocation data from the first partition with echolocation data within a third partition. The method further includes storing the combined echolocation data for all of the plurality of partitions except for the first partition in a memory.
-
公开(公告)号:US11231484B2
公开(公告)日:2022-01-25
申请号:US16816588
申请日:2020-03-12
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Karthik Subburaj , Brian Paul Ginsburg , Daniel Colum Breen , Sandeep Rao , Karthik Ramasubramanian
IPC: G01S7/40 , G01S7/03 , G01S7/35 , G01S13/931 , G01S13/02
Abstract: Methods for monitoring of performance parameters of one or more receive channels and/or one or more transmit channels of a radar system-on-a-chip (SOC) are provided. The radar SOC may include a loopback path coupling at least one transmit channel to at least one receive channel to provide a test signal from the at least one transmit channel to the at least one receive channel when the radar SOC is operated in test mode. In some embodiments, the loopback path includes a combiner coupled to each of one or more transmit channels, a splitter coupled to each of one or more receive channels, and a single wire coupling an output of the combiner to an input of the splitter.
-
公开(公告)号:US20210247488A1
公开(公告)日:2021-08-12
申请号:US17243616
申请日:2021-04-29
Applicant: Texas Instruments Incorporated
Inventor: Sandeep Rao , Saurabh Khanna
IPC: G01S7/03 , H01Q21/08 , H01Q3/26 , G01S7/35 , G01S13/931 , H01Q1/32 , G01S13/42 , H01Q3/24 , G01S13/34
Abstract: A radar apparatus for estimating position of a plurality of obstacles. The radar apparatus includes a receive antenna unit. The receive antenna unit includes a linear array of antennas and an additional antenna at a predefined offset from at least one antenna in the linear array of antennas. The radar apparatus also includes a signal processing unit. The signal processing unit estimates an azimuth frequency associated with each obstacle of the plurality of obstacles from a signal received from the plurality of obstacles at the linear array of antennas. In addition, the signal processing unit estimates an azimuth angle and an elevation angle associated with each obstacle from the estimated azimuth frequency associated with each obstacle.
-
公开(公告)号:US11023323B2
公开(公告)日:2021-06-01
申请号:US16788004
申请日:2020-02-11
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Sandeep Rao , Karthik Ramasubramanian , Brian Paul Ginsburg
Abstract: Data memory protection is provided for a signal processing system such as a radar system in which the data memory is protected with a common set of parity bits rather than requiring a set of parity bits for each memory word as in Error Correction Coded (ECC) memories. The common set of parity bits may be updated as memory words in the data memory are accessed as part of signal processing of one or more digital signals. The memory protection ensures that in the absence of memory errors the common parity bits are zero at the end of processing the digital signals as long as each word in the data memory that is used for storing the signal processing data is written and read an equal number of times.
-
公开(公告)号:US11022675B2
公开(公告)日:2021-06-01
申请号:US16857242
申请日:2020-04-24
Applicant: Texas Instruments Incorporated
Inventor: Sandeep Rao , Saurabh Khanna
IPC: G01S7/03 , G01S7/35 , G01S13/34 , G01S13/42 , G01S13/931 , H01Q3/26 , H01Q1/32 , H01Q3/24 , H01Q21/08
Abstract: A radar apparatus for estimating position of a plurality of obstacles. The radar apparatus includes a receive antenna unit. The receive antenna unit includes a linear array of antennas and an additional antenna at a predefined offset from at least one antenna in the linear array of antennas. The radar apparatus also includes a signal processing unit. The signal processing unit estimates an azimuth frequency associated with each obstacle of the plurality of obstacles from a signal received from the plurality of obstacles at the linear array of antennas. In addition, the signal processing unit estimates an azimuth angle and an elevation angle associated with each obstacle from the estimated azimuth frequency associated with each obstacle.
-
-
-
-
-
-
-
-
-