公开(公告)号：US11145622B2

公开(公告)日：2021-10-12

申请号：US16915425

申请日：2020-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen

IPC: H01L25/065 ,  H01L23/538 ,  H01L21/78 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L25/00

Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.

公开(公告)号：US11056433B2

公开(公告)日：2021-07-06

申请号：US16883210

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chen-Hua Yu

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20210202463A1

公开(公告)日：2021-07-01

申请号：US17181720

申请日：2021-02-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L25/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L21/48 ,  H01L21/56

Abstract: A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

公开(公告)号：US20210035907A1

公开(公告)日：2021-02-04

申请号：US16526983

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.

公开(公告)号：US20200235073A1

公开(公告)日：2020-07-23

申请号：US16252727

申请日：2019-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498

Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. A bonding insulating layer of the hybrid bonding structure extends to contact with one interconnect structure of the first die or the second die.

公开(公告)号：US10665540B2

公开(公告)日：2020-05-26

申请号：US16520435

申请日：2019-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Ying-Ju Chen ,  Hsien-Wei Chen ,  Der-Chyang Yeh ,  Chen-Hua Yu

IPC: H01L23/528 ,  H01L23/00 ,  H01L25/10 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065

Abstract: A method of forming an integrated circuit (IC) package with improved performance and reliability is disclosed. The method includes forming a singulated IC die, coupling the singulated IC die to a carrier substrate, and forming a routing structure. The singulated IC die has a conductive via and the conductive via has a peripheral edge. The routing structure has a conductive structure coupled to the conductive via. The routing structure further includes a cap region overlapping an area of the conductive via, a routing region having a first width from a top-down view, and an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via. The intermediate region is arranged to couple the cap region to the routing region and the second width is greater than the first width.

公开(公告)号：US20200043861A1

公开(公告)日：2020-02-06

申请号：US16601588

申请日：2019-10-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/544 ,  H01L25/065 ,  H01L23/528 ,  H01L23/522

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

公开(公告)号：US20200006324A1

公开(公告)日：2020-01-02

申请号：US16106011

申请日：2018-08-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen

IPC: H01L27/06 ,  H01L25/07 ,  H01L23/48 ,  H01L23/00

Abstract: Three-dimensional integrated circuit structures are disclosed. A three-dimensional integrated circuit structure includes a first die, a second die and a device-free die. The first die includes a first device. The second die includes a second device and is bonded to the first die. The device-free die is located aside the second die and is bonded to the first die. The device-free die includes a conductive feature electrically connected to the first die and the second die.

公开(公告)号：US20190393159A1

公开(公告)日：2019-12-26

申请号：US16016658

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/544 ,  H01L23/522 ,  H01L25/065 ,  H01L23/528

Abstract: Three-dimensional integrated circuit (3DIC) structures are disclosed. A 3DIC structure includes a first die and a second die bonded to the first die. The first die includes a first integrated circuit region and a first seal ring region around the first integrated circuit region, and has a first alignment mark within the first integrated circuit region. The second die includes a second integrated circuit region and a second seal ring region around the second integrated circuit region, and has a second alignment mark within the second seal ring region and corresponding to the first alignment mark.

公开(公告)号：US10181449B1

公开(公告)日：2019-01-15

申请号：US15717971

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jie Chen ,  Hsien-Wei Chen ,  Ying-Ju Chen

IPC: H01L23/00

Abstract: A semiconductor structure including an insulating encapsulant, a first semiconductor die, a second semiconductor die and a redistribution circuit layer is provided. The first and the second semiconductor dies embedded in the insulating encapsulant and separated from one another. The first semiconductor die includes a first active surface accessibly exposed and a first conductive terminal distributed at the first active surface. The second semiconductor die includes a second active surface accessibly exposed and a second conductive terminal distributed at the second active surface. The redistribution circuit layer including a conductive trace is disposed on the first and the second active surfaces and the insulating encapsulant. The conductive trace is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to the top width of the insulating encapsulant ranges from about 3 to about 10.