公开(公告)号：US20220262765A1

公开(公告)日：2022-08-18

申请号：US17739458

申请日：2022-05-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Jung Yang ,  Yen-Ping Wang

IPC: H01L23/00

Abstract: Packages for semiconductor devices, packaged semiconductor devices, and methods of packaging semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes an integrated circuit die mounting region, a molding material around the integrated circuit die mounting region, and an interconnect structure over the molding material and the integrated circuit die mounting region. The interconnect structure has contact pads, and connectors are coupled to the contact pads. Two or more of the connectors have an alignment feature formed thereon.

公开(公告)号：US10998293B2

公开(公告)日：2021-05-04

申请号：US16441017

申请日：2019-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Jie Chen ,  Ming-Fa Chen ,  Ching-Jung Yang

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: Semiconductor packages and methods of forming the same are disclosed. One of the methods includes the following steps. A first die is provided, wherein the first die comprises a first substrate, a first interconnect structure over the first substrate, and a first pad disposed over and electrically connected to the first interconnect structure. A first bonding dielectric layer is formed over the first die to cover the first die. By using a single damascene process, a first bonding via penetrating the first bonding dielectric layer is formed, to electrically connect the first interconnect structure.

公开(公告)号：US20210035907A1

公开(公告)日：2021-02-04

申请号：US16526983

申请日：2019-07-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Jie Chen ,  Ming-Fa Chen

IPC: H01L23/528 ,  H01L23/00 ,  H01L23/522 ,  H01L21/768 ,  H01L21/8234

Abstract: Integrated circuit devices and method of manufacturing the same are disclosed. An integrated circuit device includes an interconnect structure on a substrate, a passivation layer on the interconnect structure, a plurality of conductive pads on the passivation layer and a through interconnect via (TIV). The interconnect structure includes a plurality of dielectric layers and an interconnect in the plurality of dielectric layers. The plurality of conductive pads includes a first conductive pad electrically connecting the interconnect. The through interconnect via extends through the plurality of dielectric layers and electrically connecting a first conductive layer of the interconnect.

公开(公告)号：US20190131277A1

公开(公告)日：2019-05-02

申请号：US15939310

申请日：2018-03-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ching-Jung Yang ,  Hsien-Wei Chen

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/00 ,  H01L25/00

Abstract: Provided is a die stack structure including a first die and a second die. The first die and the second die are bonded together through a hybrid bonding structure. At least one of a first test pad of the first die or a second test pad of the second die has a protrusion of the at least one of the first test pad or the second test pad, and a bonding insulating layer of the hybrid bonding structure covers and contacts with the protrusion, so that the first test pad and the second test pad are electrically isolated from each other.

公开(公告)号：US09318456B2

公开(公告)日：2016-04-19

申请号：US14694780

申请日：2015-04-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chia Lai ,  Hsien-Ming Tu ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Chang-Pin Huang ,  Ching-Jung Yang

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/10125 ,  H01L2224/11015 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

公开(公告)号：US20210098423A1

公开(公告)日：2021-04-01

申请号：US16737856

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768

Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.

公开(公告)号：US20200098731A1

公开(公告)日：2020-03-26

申请号：US16699098

申请日：2019-11-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L23/522

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The second die includes a plurality of through-substrate vias (TSVs). The metal circuit structure is disposed over a back side of the second die. The protective structure is sandwiched between and in contact with a bottom surface of the metal circuit structure and a top surface of one of the plurality of TSVs of the second die.

公开(公告)号：US20190393194A1

公开(公告)日：2019-12-26

申请号：US16016670

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen

IPC: H01L25/065 ,  H01L21/768 ,  H01L21/56 ,  H01L23/528 ,  H01L23/00 ,  H01L25/00 ,  H01L23/48 ,  H01L23/522

Abstract: Provided is a three-dimensional integrated circuit (3DIC) structure including a die stack structure, a metal circuit structure, and a protective structure. The die stack structure includes a first die and a second die face-to-face bonded together. The metal circuit structure is disposed over a back side of the second die. The protective structure is disposed within the back side of the second die and separates one of a plurality of through-substrate vias (TSVs) of the second die from the metal circuit structure.

公开(公告)号：US20150014846A1

公开(公告)日：2015-01-15

申请号：US13940626

申请日：2013-07-12

Applicant: Taiwan Semiconductor Manufacturing Co., LTD.

Inventor： Yu-Chia Lai ,  Hsien-Ming Tu ,  Tung-Liang Shao ,  Hsien-Wei Chen ,  Chang-Pin Huang ,  Ching-Jung Yang

IPC: H01L23/00

CPC classification number: H01L24/11 ,  H01L21/563 ,  H01L23/3192 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/02235 ,  H01L2224/0225 ,  H01L2224/02255 ,  H01L2224/02313 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/024 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/10125 ,  H01L2224/11015 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2924/01029 ,  H01L2924/181 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure.

Abstract translation: 封装半导体器件包括半导体衬底，金属焊盘，金属基底，聚合物绝缘层，含铜结构和导电凸块。 金属焊盘和金属基底设置在半导体衬底上。 聚合物绝缘层覆盖金属基底和半导体基底。 含铜结构设置在聚合物绝缘层之上，并且包括支撑结构和钝化后互连（PPI）线。 支撑结构与金属基座对准。 PPI线部分地位于支撑结构内，并且通过支撑结构的开口延伸出，其中支撑结构的顶部升高到高于PPI线的顶部。 导电凸块由支撑结构保持。

公开(公告)号：US11362064B2

公开(公告)日：2022-06-14

申请号：US16737856

申请日：2020-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsien-Wei Chen ,  Ching-Jung Yang ,  Ming-Fa Chen ,  Sung-Feng Yeh ,  Ying-Ju Chen

IPC: H01L25/065 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

Abstract: A package structure includes a first die, a second die, an insulation structure, a through via, a dielectric layer and a redistribution layer. The second die is electrically bonded to the first die. The insulation structure is disposed on the first die and laterally surrounds the second die. The through via penetrates through the insulation structure to electrically connect to the first die. The through via includes a first barrier layer and a conductive post on the first barrier layer. The dielectric layer is on the second die and the insulation structure. The redistribution layer is embedded in the dielectric layer and electrically connected to the through via. The redistribution layer includes a second barrier layer and a conductive layer on the second barrier layer. The conductive layer of the redistribution layer is in contact with the conductive post of the through via.