公开(公告)号：US20200279853A1

公开(公告)日：2020-09-03

申请号：US16876416

申请日：2020-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/10 ,  H01L21/8234 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin; forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure; patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin; forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.

公开(公告)号：US20200135883A1

公开(公告)日：2020-04-30

申请号：US16258408

申请日：2019-01-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi YEONG ,  Chi-On CHUI ,  Bo-Feng YOUNG ,  Bo-Yu LAI ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L29/66 ,  H01L29/08

Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate, and a gate structure formed over the fin structure. The FinFET device structure also includes an epitaxial source/drain (S/D) structure formed over the fin structure. A top surface and a sidewall of the fin structure are surrounded by the epitaxial S/D structure. A first distance between an outer surface of the epitaxial S/D structure and the sidewall of the fin structure is no less than a second distance between the outer surface of the epitaxial S/D structure and the top surface of the fin structure.

公开(公告)号：US20200058556A1

公开(公告)日：2020-02-20

申请号：US16103704

申请日：2018-08-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Shi-Ning JU ,  Kuan-Lun CHENG ,  Chih-Hao WANG

IPC: H01L21/8234 ,  H01L27/088

Abstract: A semiconductor device includes a semiconductor substrate, a first fin structure and a second fin structure. The first fin structure includes a first fin and at least two first nano wires disposed above the first fin, and the first fin protrudes from the semiconductor substrate. The second fin structure includes a second fin and at least two second nano wires disposed above the second fin, and the second fin protrudes from the semiconductor substrate. Each first nano wire has a first width different from a second width of each second nano wire.

公开(公告)号：US20190229201A1

公开(公告)日：2019-07-25

申请号：US16373988

申请日：2019-04-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao WU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/762 ,  H01L27/12

Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor strip over a substrate. The semiconductor strip includes a first semiconductor stack and a second semiconductor stack over the first semiconductor stack. A dummy gate stack is formed to cross the semiconductor strip. The dummy gate stack is replaced with a first metal gate stack and a second metal gate stack. The first metal gate stack is in contact with the first semiconductor layer of the first semiconductor stack and the second metal gate stack is in contact with the first semiconductor layer of the second semiconductor stack.

公开(公告)号：US20190165127A1

公开(公告)日：2019-05-30

申请号：US15883684

申请日：2018-01-30

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Kuan-Lun CHENG ,  Chih-Hao WANG ,  Keng-Chu LIN ,  Shi-Ning JU

IPC: H01L29/66 ,  H01L29/06 ,  H01L27/088 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: A semiconductor device is disclosed that includes a plurality of isolation regions. A fin is arranged between the plurality of isolation regions. One of the plurality of isolation regions includes a first atomic layer deposition (ALD) layer, a second ALD layer, a flowable chemical vapor deposition (FCVD) layer, and a third ALD layer. The first ALD layer includes a first trench. The second ALD layer is formed in the first trench of the first ALD layer. The FCVD layer is formed in the first trench of the first ALD layer and on the second ALD layer. The third ALD layer is formed on the FCVD layer.

公开(公告)号：US20190097011A1

公开(公告)日：2019-03-28

申请号：US15716699

申请日：2017-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wei-Hao WU ,  Zhi-Chang LIN ,  Ting-Hung HSU ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/12

Abstract: A semiconductor device includes a substrate, a first device with a horizontal-gate-all-around configuration, and a second device with a horizontal-gate-all-around configuration. The first device is over the substrate. The second device is over the first device. A channel of the first device is between the substrate and a channel of the second device.

公开(公告)号：US20190096765A1

公开(公告)日：2019-03-28

申请号：US15718740

申请日：2017-09-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Kuan-Lun CHENG

IPC: H01L21/8234 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6681

Abstract: The present disclosure describes a method to reduce power consumption in a fin structure. For example, the method includes forming a first and a second semiconductor fins on a substrate with different heights. The method also includes forming insulating fins between and adjacent to the first and the second semiconductor fins. Further, the method includes forming a first and second epitaxial stacks with different heights on each of the first and second semiconductor fins.

公开(公告)号：US20190067448A1

公开(公告)日：2019-02-28

申请号：US15857196

申请日：2017-12-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/45

CPC classification number: H01L29/66545 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/28114 ,  H01L21/3065 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a fin field effect transistors (finFET) on a substrate includes forming a fin structure on the substrate, forming a protective layer on the fin structure, and forming a polysilicon structure on the protective layer. The method further includes modifying the polysilicon structure such that a first horizontal dimension of a first portion of the modified polysilicon structure is smaller than a second horizontal dimension of a second portion of the modified polysilicon structure. The method further includes replacing the modified polysilicon structure with a gate structure having a first horizontal dimension of a first portion of the gate structure that is smaller than a second horizontal dimension of a second portion of the gate structure.

公开(公告)号：US20190027570A1

公开(公告)日：2019-01-24

申请号：US15653068

申请日：2017-07-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng CHING ,  Chih-Hao WANG ,  Ching-Wei TSAI ,  Kuan-Lun CHENG

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/165

Abstract: In accordance with an aspect of the present disclosure, in a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed. A sacrificial gate structure is formed over the fin structure. A first cover layer is formed over the sacrificial gate structure, and a second cover layer is formed over the first cover layer. A source/drain epitaxial layer is formed. After the source/drain epitaxial layer is formed, the second cover layer is removed, thereby forming a gap between the source/drain epitaxial layer and the first cover layer, from which a part of the fin structure is exposed. Part of the first semiconductor layers is removed in the gap, thereby forming spaces between the second semiconductor layers. The spaces are filled with a first insulating material.

公开(公告)号：US20190006371A1

公开(公告)日：2019-01-03

申请号：US15905905

申请日：2018-02-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tetsu OHTOU ,  Ching-Wei TSAI ,  Kuan-Lun CHENG ,  Yasutoshi OKUNO ,  Jiun-Jia HUANG

IPC: H01L27/11 ,  H01L27/088 ,  H01L29/10 ,  H01L29/06 ,  H01L21/8234

Abstract: A semiconductor device includes a substrate having a semiconductor fin, in which the semiconductor fin has a first sidewall and a second sidewall opposite to the first sidewall; an epitaxy structure in contact with the first sidewall of the semiconductor fin; and a spacer in contact with the second sidewall of the semiconductor fin and the epitaxy structure.