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    Semiconductor integrated circuit
    91.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20060044871A1

    公开(公告)日：2006-03-02

    申请号：US11195684

    申请日：2005-08-03

    Applicant: Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

    Inventor： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

    IPC: G11C16/06

    CPC classification number: G11C16/344

    Abstract: The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

    Abstract translation: 本发明旨在实现更高的读取速度和对非易失性存储器的更大数量的重写时间的保证。 半导体集成电路具有第一非易失性存储区域和用于根据变化的阈值电压存储信息的第二非易失性存储区域。 擦除验证存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间中的一个或多个条件 第一非易失性存储器区域与第二非易失性存储区域中的那些不同，第一非易失性存储区域中存储的读取信息的速度高于存储在第二非易失性存储区域中的读取信息的速度，并且确定的数量 在第二非易失性存储器区域中的重写次数大于第一非易失性存储器区域中的重写时间。

    Stereoregular polymer and monomer thereof and process for production of both
    92.
    发明申请
    Stereoregular polymer and monomer thereof and process for production of both 失效
    立体定向聚合物及其单体及其制备方法

    公开(公告)号：US20060009601A1

    公开(公告)日：2006-01-12

    申请号：US10513756

    申请日：2003-05-08

    Applicant: Akikazu Matsumoto ,  Toshihiro Tanaka

    Inventor： Akikazu Matsumoto ,  Toshihiro Tanaka

    IPC: C08F20/20

    CPC classification number: C08F2/48 ,  C07C67/11 ,  C07C69/602 ,  C07C69/65 ,  C08F36/14

    Abstract: An ester derivant having a crystal structure in which the molecules in two adjacent molecule planes are antiparallel is created from a carboxylic acid having carbon-carbon double bond and a compound having a functional group that can react to a carboxyl group of the carboxylic acid. The crystal of the ester derivant is then subjected to light irradiation or heating.

    Abstract translation: 由具有碳 - 碳双键的羧酸和具有能够与羧酸的羧基反应的官能团的化合物产生具有两相邻分子平面中的分子反平行的晶体结构的酯衍生物。 然后将酯衍生物的晶体进行光照射或加热。

    Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system
    94.
    发明授权
    Nonvolatile semiconductor memory, data deletion method of nonvolatile semiconductor memory, information processing apparatus and nonvolatile semiconductor memory system 失效
    非易失性半导体存储器，非易失性半导体存储器的数据删除方法，信息处理装置和非易失性半导体存储器系统

    公开(公告)号：US06747895B2

    公开(公告)日：2004-06-08

    申请号：US10083602

    申请日：2002-02-27

    Applicant: Yukiko Umemoto ,  Toshihiro Tanaka ,  Hiroyuki Tanikawa ,  Yutaka Shinagawa

    Inventor： Yukiko Umemoto ,  Toshihiro Tanaka ,  Hiroyuki Tanikawa ,  Yutaka Shinagawa

    IPC: G11C1604

    CPC classification number: G11C16/3445 ,  G11C8/12 ,  G11C16/16 ,  G11C2216/18

    Abstract: This inventing is intended to shorten data deletion time of a nonvolatile semiconductor memory such as a flash memory (EEPROM). When deleting data written to a memory cell MC0 among flash memory cells MC0 to MC2 formed on a semiconductor substrate PSUB through a separation region NiSO, a voltage of p type well PWL0 in which the memory cell MC0 is formed is raised to 10V and a voltage of the separation region NiSO is raised to 12V by using a voltage application unit different from a voltage application unit applying a voltage to the p type well PWL0. As a result, parasitic capacitances Ca1 and Ca2 generated between p type wells PWL1 and PWL2 in which the unselected memory cells MC1 and MC2 are formed and the separation region NiSO, respectively, and a parasitic capacitance Cb generated between the separation region NiSO and the semiconductor substrate PSUB are charged by the voltage application units. It is, therefore, possible to shorten time required to charge the parasitic capacitances and to shorten the deletion time.

    Abstract translation: 本发明旨在缩短诸如闪速存储器（EEPROM）的非易失性半导体存储器的数据删除时间。 当通过分离区域NiSO删除在半导体衬底PSUB上形成的闪存单元MC0至MC2中写入存储单元MC0的数据时，形成存储单元MC0的p型阱PWL0的电压升高到10V， 通过使用与向p型阱PWL0施加电压的电压施加单元不同的电压施加单元将NiSO升高到12V。 结果，在形成未选择的存储单元MC1和MC2的p型阱PWL1和PWL2之间分别产生的寄生电容Ca1和Ca2分别与分离区NiSO和半导体之间产生的寄生电容Cb 基板PSUB由电压施加单元充电。 因此，可以缩短为寄生电容充电所需的时间并缩短删除时间。

    Electrically erasable and programmable nonvolatile semiconductor memory
    96.
    发明授权
    Electrically erasable and programmable nonvolatile semiconductor memory 有权
    电可擦除和可编程的非易失性半导体存储器

    公开(公告)号：US06201735B1

    公开(公告)日：2001-03-13

    申请号：US09362719

    申请日：1999-07-29

    Applicant: Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

    Inventor： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

    IPC: G11C1604

    CPC classification number: G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

    Abstract: Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage is applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

    Abstract translation: 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 此外，因为负电压被施加到字线，所以可以降低编程数据时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

    Semiconductor memory system with the function of the replacement to the other chips
    98.
    发明授权
    Semiconductor memory system with the function of the replacement to the other chips 失效
    半导体存储系统具有替代其他芯片的功能

    公开(公告)号：US5469390A

    公开(公告)日：1995-11-21

    申请号：US301284

    申请日：1994-09-06

    Applicant: Toshio Sasaki ,  Toshihiro Tanaka

    Inventor： Toshio Sasaki ,  Toshihiro Tanaka

    IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

    CPC classification number: G11C29/808

    Abstract: In a semiconductor memory system including a plurality of memory chips, a spare memory is shared among the memory chips. For such a purpose, a common redundant circuit and an external terminal capable of accessing to a spare memory are added to a semiconductor memory system, and a first region for storing a defect address in each memory of the semiconductor memory system and a second region for storing a defect address of the system of the object having the same structure as the first region are provided in the redundant circuit. With this, even when the defect of a normal memory of the semiconductor memory system can not be replaced with the spare memory of the system itself, replacement is made possible with other system having the same structure. Accordingly, the yield of the semiconductor memory system can be increased, and the reliability is also increased.

    Abstract translation: 在包括多个存储器芯片的半导体存储器系统中，在存储器芯片之间共享备用存储器。 为了这样的目的，能够访问备用存储器的公共冗余电路和外部终端被添加到半导体存储器系统中，并且第一区域用于在半导体存储器系统的每个存储器中存储缺陷地址，第二区域用于 存储具有与第一区域相同结构的对象的系统的缺陷地址设置在冗余电路中。 由此，即使半导体存储器系统的正常存储器的缺陷不能用系统本身的备用存储器替换，也可以用具有相同结构的其他系统进行替换。 因此，可以提高半导体存储器系统的产量，并且还提高可靠性。

    Non-volatile memory programming at arbitrary timing based on current requirements
    99.
    发明授权
    Non-volatile memory programming at arbitrary timing based on current requirements 失效
    基于当前要求的任意定时的非易失性存储器编程

    公开(公告)号：US5422856A

    公开(公告)日：1995-06-06

    申请号：US203303

    申请日：1994-03-01

    Applicant: Toshio Sasaki ,  Toshihiro Tanaka ,  Masataka Kato

    Inventor： Toshio Sasaki ,  Toshihiro Tanaka ,  Masataka Kato

    IPC: G06F12/06 ,  G06F12/00 ,  G11C16/02 ,  G11C16/10 ,  G11C17/00 ,  G11C8/00

    CPC classification number: G11C16/102

    Abstract: To effect erase and program operations, i.e., rewrite of the non-volatile memory device efficiently with small electric power consumption and at high speed, a plurality of memory blocks that have a plurality of sectors and that each include a plurality of non-volatile memory cells are connected to buffer memories having at least the same memory capacity as a sector, and a read/write circuit generates internal addresses and timing for selecting sectors according to the external address and timing signals to control the read-out and rewrite of data between the sectors corresponding to the internal addresses and the buffer memories corresponding to the sectors, wherein the read/write circuit selects the sectors at timings shifted from one another and erases or programs the data in the selected sector in order to rewrite the data.

    Abstract translation: 为了实现擦除和编程操作，即以小功耗和高速度有效地重写非易失性存储器件，具有多个扇区的多个存储器块，并且每个存储块中的每一个包括多个非易失性存储器 单元被连接到具有至少与扇区相同的存储容量的缓冲存储器，并且读/写电路根据外部地址和定时信号产生用于选择扇区的内部地址和定时，以控制数据的读出和重写 对应于内部地址的扇区和对应于扇区的缓冲存储器，其中读/写电路在彼此偏移的定时中选择扇区，并擦除或编程所选扇区中的数据，以重写数据。

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