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    Semiconductor device including resistance storage element
    2.
    发明授权
    Semiconductor device including resistance storage element 有权
    包括电阻存储元件的半导体器件

    公开(公告)号：US07881102B2

    公开(公告)日：2011-02-01

    申请号：US12370283

    申请日：2009-02-12

    申请人： Fumihiko Nitta ,  Yoshikazu Iida ,  Takashi Yamaki

    发明人： Fumihiko Nitta ,  Yoshikazu Iida ,  Takashi Yamaki

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0076 ,  G11C2213/79

    摘要： A phase change memory includes a memory cell with a phase change element storing data according to level change of a resistance value in association with phase change, a write circuit converting the phase change element to an amorphous state or a polycrystalline state according to the logic of write data in a write operation mode, a read circuit reading out stored data from the phase change element in a readout operation mode, and a discharge circuit applying a discharge voltage to the phase change element to remove electrons trapped in the phase change element in a discharge operation mode. Accordingly, variation in the resistance value at the phase change element can be suppressed.

    摘要翻译： 相变存储器包括具有相变元件的存储单元，该相变元件根据与相变相关联的电阻值的电平变化存储数据，写入电路根据逻辑将逻辑转换为非晶态或多晶态 在写入操作模式下写入数据，读出电路在读出操作模式下从相变元件读出存储的数据，以及放电电路将放电电压施加到相变元件，以去除捕获在相变元件中的电子 放电操作模式。 因此，可以抑制相变元件的电阻值的变化。

    Semiconductor integrated circuit
    4.
    发明申请
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US20060044871A1

    公开(公告)日：2006-03-02

    申请号：US11195684

    申请日：2005-08-03

    申请人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

    发明人： Hiroyuki Tanikawa ,  Toshihiro Tanaka ,  Yutaka Shinagawa ,  Takashi Yamaki

    IPC分类号： G11C16/06

    CPC分类号： G11C16/344

    摘要： The present invention is directed to realize both higher reading speed and assurance of the larger number of rewriting times for a nonvolatile memory. A semiconductor integrated circuit has a first nonvolatile memory area and a second nonvolatile memory area for storing information in accordance with a threshold voltage which varies. One or plural conditions out of erase verify determination memory gate voltage, erase verify determination memory current, write verify determination memory gate voltage, write verify determination memory current, erase voltage, erase voltage application time, write voltage, and write voltage application time in the first nonvolatile memory area is/are made different from that/those in the second nonvolatile memory area, speed of reading information stored in the first nonvolatile memory area is higher than that of reading information stored in the second nonvolatile memory area, and the assured number of rewriting times in the second nonvolatile memory area is larger than that in the first nonvolatile memory area.

    摘要翻译： 本发明旨在实现更高的读取速度和对非易失性存储器的更大数量的重写时间的保证。 半导体集成电路具有第一非易失性存储区域和用于根据变化的阈值电压存储信息的第二非易失性存储区域。 擦除验证存储器栅极电压，擦除验证确定存储器电流，写入验证确定存储器栅极电压，写入验证确定存储器电流，擦除电压，擦除电压施加时间，写入电压和写入电压施加时间中的一个或多个条件 第一非易失性存储器区域与第二非易失性存储区域中的那些不同，第一非易失性存储区域中存储的读取信息的速度高于存储在第二非易失性存储区域中的读取信息的速度，并且确定的数量 在第二非易失性存储器区域中的重写次数大于第一非易失性存储器区域中的重写时间。

    Semiconductor integrated circuit device
    6.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08385134B2

    公开(公告)日：2013-02-26

    申请号：US13244448

    申请日：2011-09-24

    申请人： Takashi Yamaki

    发明人： Takashi Yamaki

    IPC分类号： G11C7/06

    CPC分类号： G11C5/147 ,  G11C11/417

    摘要： When a leakage type determining circuit determines that leakage current components of a gate leakage and a substrate leakage are larger in a resume standby mode, a VDDR regulator generates a power supply voltage VDDR at a first voltage level lower than a power supply voltage VDD, and supplies the voltage as a power supply voltage VDDR1 to an SRAM module via a selector switch. When the leakage type determining circuit determines that a leakage current of a channel leakage is larger, the VDDR regulator supplies the power supply voltage VDDR1 higher than the first voltage level and lower than the power supply voltage VDD to the SRAM module. Also, an ARVSS regulator supplies a cell source power supply voltage higher than a reference voltage to an SRAM module in another region.

    摘要翻译： 当泄漏型确定电路在恢复待机模式下确定栅极泄漏和衬底泄漏的漏电流分量较大时，VDDR调节器产生低于电源电压VDD的第一电压电平的电源电压VDDR，以及 通过选择开关将电压作为电源电压VDDR1提供给SRAM模块。 当泄漏型判定电路判定为漏电流的漏电流较大时，VDDR调节器将高于第一电压电平的电源电压VDDR1提供给低于VDD模块的电源电压VDD。 此外，ARVSS调节器将高于参考电压的单元电源电源电压提供给另一区域中的SRAM模块。

    SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130021832A1

    公开(公告)日：2013-01-24

    申请号：US13532107

    申请日：2012-06-25

    申请人： Takashi YAMAKI

    发明人： Takashi YAMAKI

    IPC分类号： G11C5/02

    CPC分类号： G11C11/419 ,  G06F1/26 ,  G06F3/0604 ,  G06F3/0629 ,  G06F3/067 ,  G11C5/148 ,  G11C7/22 ,  G11C11/413 ,  G11C11/417 ,  G11C11/418 ,  G11C2207/2227

    摘要： In a semiconductor device, memory modules each having a low power consumption mode that is enabled and disabled by a control signal belong to a memory block. A transmission path of the control signal is provided such that the control signal is inputted in parallel to the memory module via an inside-of-module path, and such that the control signal is outputted by a particular memory module of the memory modules via the inside-of-module path to a downstream outside-of-module path. The particular memory module in the memory block is selected such that it has a greater storage capacity than the other memory modules belonging to this same memory block have.

    摘要翻译： 在半导体装置中，各自具有由控制信号启用和禁用的低功耗模式的存储器模块属于存储块。 提供控制信号的传输路径，使得控制信号经由内部模块路径并行地输入到存储器模块，并且使得控制信号由存储器模块的特定存储器模块经由 模块内部路径到模块下游的路径。 选择存储器块中的特定存储器模块使得其具有比属于该相同存储器块的其它存储器模块更大的存储容量。

    Nonvolatile memory device and semiconductor device
    10.
    发明授权
    Nonvolatile memory device and semiconductor device 有权
    非易失性存储器件和半导体器件

    公开(公告)号：US07529126B2

    公开(公告)日：2009-05-05

    申请号：US11472993

    申请日：2006-06-23

    申请人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    发明人： Toshihiro Tanaka ,  Takashi Yamaki ,  Yutaka Shinagawa ,  Daisuke Okada ,  Digh Hisamoto ,  Kan Yasui ,  Tetsuya Ishimaru

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/10 ,  G11C16/0433

    摘要： Disclosed here is a method for speeding up data writing and reducing power consumption by reducing the variation of the threshold voltage of each of non-volatile memory cells at data writing. When writing data in a memory cell, a voltage of about 8V is applied to the memory gate line, a voltage of about 5V is applied to the source line, a voltage of about 1.5V is applied to the selected gate line respectively. At that time, in the writing circuit, the writing pulse is 0, the writing latch output a High signal, and a NAND-circuit outputs a Low signal. And, a constant current of about 1iA flows in a constant current source transistor and the bit line is discharged by a constant current of about 1iA to flow a current in the memory cell.

    摘要翻译： 这里公开了一种通过在数据写入时减小每个非易失性存储单元的阈值电压的变化来加速数据写入并降低功耗的方法。 当在存储单元中写入数据时，约8V的电压被施加到存储器栅极线，大约5V的电压被施加到源极线，大约1.5V的电压分别施加到所选择的栅极线。 此时，在写入电路中，写入脉冲为0，写入锁存器输出高电平信号，NAND电路输出低电平信号。 并且，在恒定电流源晶体管中流动约1iA的恒定电流，并且通过约1iA的恒定电流放电位线以使存储单元中的电流流动。