公开(公告)号：US07144777B2

公开(公告)日：2006-12-05

申请号：US11066994

申请日：2005-02-25

申请人： Tzung-Han Lee ,  Wen-Jeng Lin ,  Kuang-Pi Lee ,  Blue Larn

发明人： Tzung-Han Lee ,  Wen-Jeng Lin ,  Kuang-Pi Lee ,  Blue Larn

IPC分类号： H01L21/336

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/6653

摘要： A non-volatile memory comprising a substrate, a stacked gate structure, a conductive spacer, an oxide/nitride/oxide layer, buried doping regions, a control gate and an insulating layer. The stacked gate structure is disposed on the substrate. The stacked gate structure comprises a gate dielectric layer, a select gate and a cap layer. The conductive spacer is disposed on the sidewalls of the stacked gate structure. The oxide/nitride/oxide layer is disposed between the conductive spacer and the stacked gate structure and between the conductive spacer and the substrate. The buried doping regions are disposed in the substrate outside the conductive spacer on each side of the stacked gate structure. The control gate is disposed over the stacked gate structure and electrically connected to the conductive spacer. The insulating layer is disposed between the buried doping layer and the control gate.

摘要翻译： 包括衬底，堆叠栅极结构，导电间隔物，氧化物/氮化物/氧化物层，掩埋掺杂区域，控制栅极和绝缘层的非易失性存储器。 层叠的栅极结构设置在基板上。 堆叠栅极结构包括栅极介电层，选择栅极和盖层。 导电间隔物设置在堆叠栅结构的侧壁上。 氧化物/氮化物/氧化物层设置在导电间隔物和层叠栅极结构之间以及导电间隔物和衬底之间。 掩埋掺杂区域设置在层叠栅极结构的每一侧上的导电间隔物外部的衬底中。 控制栅极设置在堆叠的栅极结构上并电连接到导电间隔物。 绝缘层设置在掩埋掺杂层和控制栅之间。

公开(公告)号：US20060250777A1

公开(公告)日：2006-11-09

申请号：US11123105

申请日：2005-05-06

申请人： Yun-Chen Chen ,  Tzung-Han Lee

发明人： Yun-Chen Chen ,  Tzung-Han Lee

IPC分类号： H05K7/16

CPC分类号： G06F1/26 ,  G06F1/188

摘要： A loading and unloading mechanism adopted for use on removable power supply modules includes in one embodiment a connection plug installed on a removable power supply and a connection trough connected to a power supply circuit of a system end (such as a personal computer). Another embodiment includes a connection trough on a system end to be installed on a holding unit which is movable to adjust the position relative to the system end according to the size of the removable power supply so that the removable power supply can be fully loaded into the computer. The loading and unloading mechanism thus formed can be adapted for the removable power supply of varying sizes and specifications.

摘要翻译： 在可移动电源模块中使用的装载和卸载机构包括在一个实施例中，安装在可拆卸电源上的连接插头和连接到系统端（例如个人计算机）的电源电路的连接槽。 另一个实施例包括在系统端上的连接槽，该连接槽将安装在保持单元上，该保持单元可移动以根据可拆卸电源的尺寸来调节相对于系统端的位置，使得可移除的电源可以完全装入 电脑。 如此形成的装卸机构可适用于不同尺寸和规格的可拆卸电源。

公开(公告)号：US20060202247A1

公开(公告)日：2006-09-14

申请号：US11416699

申请日：2006-05-02

申请人： Tzung-Han Lee ,  Kuang-Pi Lee ,  Wen-Jeng Lin ,  Rern-Hurng Larn

发明人： Tzung-Han Lee ,  Kuang-Pi Lee ,  Wen-Jeng Lin ,  Rern-Hurng Larn

IPC分类号： H01L29/94

CPC分类号： H01L27/1087 ,  H01L27/11 ,  Y10S257/903

摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

摘要翻译： 至少包括衬底，晶体管，上电极和电容器电介质层的静态随机存取存储器（SRAM）单元结构。 在衬底中设置器件隔离结构以限定有源区。 活动区域有一个开口。 晶体管设置在衬底的有源区上。 晶体管的源极区域靠近开口。 将上电极设置在开口上方，使得开口完全充满。 电容器介电层设置在上电极和衬底之间。

公开(公告)号：US20060197132A1

公开(公告)日：2006-09-07

申请号：US11416925

申请日：2006-05-02

申请人： Tzung-Han Lee ,  Kuang-Pi Lee ,  Wen-Jeng Lin ,  Rern-Hurng Larn

发明人： Tzung-Han Lee ,  Kuang-Pi Lee ,  Wen-Jeng Lin ,  Rern-Hurng Larn

IPC分类号： H01L29/94

CPC分类号： H01L27/1087 ,  H01L27/11 ,  Y10S257/903

摘要： A static random access memory (SRAM) cell structure at least comprising a substrate, a transistor, an upper electrode and a capacitor dielectric layer. A device isolation structure is set up in the substrate to define an active region. The active region has an opening. The transistor is set up over the active region of the substrate. The source region of the transistor is next to the opening. The upper electrode is set up over the opening such that the opening is completely filled. The capacitor dielectric layer is set up between the upper electrode and the substrate.

摘要翻译： 至少包括衬底，晶体管，上电极和电容器介电层的静态随机存取存储器（SRAM）单元结构。 在衬底中设置器件隔离结构以限定有源区。 活动区域有一个开口。 晶体管设置在衬底的有源区上。 晶体管的源极区域靠近开口。 将上电极设置在开口上方，使得开口完全充满。 电容器介电层设置在上电极和衬底之间。

公开(公告)号：US20050275991A1

公开(公告)日：2005-12-15

申请号：US10853164

申请日：2004-05-26

申请人： Tzung-Han Lee

发明人： Tzung-Han Lee

IPC分类号： G06F1/18 ,  H02H5/04

CPC分类号： G06F1/184 ,  G06F1/188

摘要： A power supply having an extendable power input port connecting to a connection line to be installed on a side wall of a computer host. The side wall and the power supply form a heat dissipation passage therebetween to improve heated airflow in the computer host and increase heat dissipation effect without affecting electric plugging of the power supply.

摘要翻译： 一种电源，具有连接到要安装在计算机主机的侧壁上的连接线的可延伸电源输入端口。 侧壁和电源在其间形成散热通道，以改善计算机主机中的加热气流并增加散热效果，而不影响电源的电插塞。

公开(公告)号：US06316352B1

公开(公告)日：2001-11-13

申请号：US09704189

申请日：2000-11-01

申请人： King-Lung Wu ,  Tzung-Han Lee

发明人： King-Lung Wu ,  Tzung-Han Lee

IPC分类号： H01L214763

CPC分类号： H01L28/92 ,  H01L21/76895 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A method of fabricating a bottom electrode is described. A substrate having a first conductive layer therein is provided. A first dielectric layer is formed over the substrate. A plurality bit lines is formed over the first dielectric layer. A conformal liner layer is formed over the first dielectric layer to cover the plurality bit lines. A second dielectric layer is formed over the conformal liner layer. An opening is formed in the second dielectric layer. The opening exposes a portion of the conformal liner layer between the bit lines and the conformal liner layer on portions of the bit lines. A conductive spacer is formed on a sidewall of the opening to expose a portion of the conformal liner layer between the bit lines. The exposed portion of the conformal liner layer between the bit lines is removed. The first dielectric layer exposed by the conductive spacer and the second dielectric layer are removed to form a node contact opening in the first dielectric layer. The node contact opening exposes the conductive layer. A second conductive layer is formed to fill the node contact opening.

摘要翻译： 描述制造底部电极的方法。 提供了其中具有第一导电层的衬底。 第一电介质层形成在衬底上。 多个位线形成在第一介电层上。 在第一介电层上形成保形衬层以覆盖多个位线。 第二电介质层形成在保形衬里层上。 在第二电介质层中形成开口。 开口在位线的一部分上的位线和共形衬垫层之间露出共形衬垫层的一部分。 导电间隔件形成在开口的侧壁上以暴露位线之间的共形内衬层的一部分。 位线之间的共形衬垫层的暴露部分被去除。 去除由导电间隔物和第二介电层暴露的第一电介质层，以在第一电介质层中形成节点接触开口。 节点接触开口露出导电层。 形成第二导电层以填充节点接触开口。

公开(公告)号：US06261968B1

公开(公告)日：2001-07-17

申请号：US09497669

申请日：2000-02-04

申请人： Tzung-Han Lee

发明人： Tzung-Han Lee

IPC分类号： H01L21302

CPC分类号： H01L21/76897 ,  H01L21/31144

摘要： The present invention provides a method of forming a self-aligned contact hole on a semiconductor wafer. The semiconductor wafer comprises a substrate, two gates positioned on the substrate, at least a doped area between the gates on the substrate and spacers on each of two opposite walls of each gate wherein the spacers between the gates are joined and cover the doped area. The method comprises forming a dielectric layer on the surface of the semiconductor wafer, the dielectric layer covering the gates and the spacers. A first etching process is performed to remove the dielectric layer above the doped area down to a predetermined depth to form an opening, the bottom of the opening comprising the spacers and an upper portion of the gates. Poly-silicon spacers are then formed on the interior walls of the opening, the poly-silicon spacers covering an upper portion of the spacers and the upper portion of the gates. A second etching process is performed to remove from between the poly-silicon spacers both the remaining dielectric layer and a lower portion of the spacers down to the surface of the doped area.

摘要翻译： 本发明提供一种在半导体晶片上形成自对准接触孔的方法。 半导体晶片包括衬底，位于衬底上的两个栅极，至少衬底上的栅极之间的掺杂区域和每个栅极的两个相对壁中的每一个上的间隔物，其中栅极之间的间隔物被接合并覆盖掺杂区域。 该方法包括在半导体晶片的表面上形成介电层，覆盖栅极和间隔物的电介质层。 执行第一蚀刻工艺以将掺杂区域上方的电介质层去除到预定深度以形成开口，开口的底部包括间隔件和栅极的上部。 然后在开口的内壁上形成多晶硅间隔物，多晶硅间隔物覆盖间隔物的上部和栅极的上部。 执行第二蚀刻工艺以将剩余介电层和间隔物的下部的多晶硅间隔物从多晶硅间隔物向下移动到掺杂区域的表面。

公开(公告)号：US6165879A

公开(公告)日：2000-12-26

申请号：US426979

申请日：1999-10-26

申请人： Tzung-Han Lee ,  Hsi-Chien Lin

发明人： Tzung-Han Lee ,  Hsi-Chien Lin

IPC分类号： H01L21/60 ,  H01L21/3205

CPC分类号： H01L21/76897

摘要： The invention is related to a method for increasing margin precision of a self-aligned contact. A semiconductor has at least a gate electrode and source/drain, and a gate spacer is formed on the sidewall of the gate electrode. A first silicon oxide layer is then formed on the semiconductor substrate. A hard mask layer is formed on the first silicon oxide layer. A second silicon oxide layer is then deposited over the hard mask layer. A chemical mechanical polishing is then performed to remove the second silicon oxide layer so that the hard mask layer is planarized. Thereafter, the hard mask layer and the first silicon oxide layer is etched to form a gap region on the first silicon oxide layer. A polysilicon layer is then deposited over the entire substrate including the gap region and the hard mask layer. Thereafter, the polysilicon layer is etched back to form a polysilicon spacer. Finally, the gap region of the first silicon oxide layer is etched to form a self-aligned contact.

摘要翻译： 本发明涉及一种用于增加自对准接触的裕量精度的方法。 半导体至少具有栅电极和源极/漏极，并且栅极间隔物形成在栅电极的侧壁上。 然后在半导体衬底上形成第一氧化硅层。 在第一氧化硅层上形成硬掩模层。 然后在硬掩模层上沉积第二氧化硅层。 然后执行化学机械抛光以除去第二氧化硅层，使得硬掩模层被平坦化。 此后，蚀刻硬掩模层和第一氧化硅层，以在第一氧化硅层上形成间隙区域。 然后在包括间隙区域和硬掩模层的整个基板上沉积多晶硅层。 此后，多晶硅层被回蚀以形成多晶硅间隔物。 最后，蚀刻第一氧化硅层的间隙区域以形成自对准接触。