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253 条记录 (耗时 0.047 秒)

    Oversubscribing Bandwidth In A Communications Network
    93.
    发明申请
    Oversubscribing Bandwidth In A Communications Network 有权
    在通信网络中超频带宽

    公开(公告)号：US20090097404A1

    公开(公告)日：2009-04-16

    申请号：US12272711

    申请日：2008-11-17

    申请人： Philippe Damon ,  Claude Basso ,  Jean L. Calvignac ,  Francis Arts ,  Pierre L. Debuysscher

    发明人： Philippe Damon ,  Claude Basso ,  Jean L. Calvignac ,  Francis Arts ,  Pierre L. Debuysscher

    IPC分类号： H04L12/24 ,  G01R31/08

    CPC分类号： H04L47/10 ,  H04L47/20

    摘要： A system and computer readable medium for oversubscribing bandwidth in a communication network, is disclosed. The system and computer readable medium includes policing a first data flow and outputting a first output data flow from the first meter, in relation to a first Committed Information Rate (CIR) and a first Peak Information Rate (PIR); policing a second data flow and outputting a second output data flow from the second meter in relation to a second CIR and a second PIR; and policing an aggregated output data flow of the first output data flow and the second output data through a third meter of the oversubscription module, where the aggregated output data flow is policed in relation to a third CIR and a third PIR.

    摘要翻译： 公开了一种在通信网络中超额订购带宽的系统和计算机可读介质。 系统和计算机可读介质包括对第一数据流进行管理，并相对于第一承诺信息速率（CIR）和第一峰值信息速率（PIR）从第一仪表输出第一输出数据流; 管理第二数据流，并相对于第二CIR和第二PIR从第二计量器输出第二输出数据流; 以及通过所述超额预订模块的第三计量管理所述第一输出数据流和所述第二输出数据的聚合输出数据流，其中所述聚合输出数据流相对于第三CIR和第三PIR进行监管。

    Structure for scheduler pipeline design for hierarchical link sharing
    96.
    发明授权
    Structure for scheduler pipeline design for hierarchical link sharing 失效
    用于分层链路共享的调度器流水线设计的结构

    公开(公告)号：US07457241B2

    公开(公告)日：2008-11-25

    申请号：US10772737

    申请日：2004-02-05

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    IPC分类号： H04J1/16

    CPC分类号： H04L47/60 ,  H04L47/15 ,  H04L47/50 ,  H04L47/52 ,  H04L49/90

    摘要： A pipeline configuration is described for use in network traffic management for the hardware scheduling of events arranged in a hierarchical linkage. The configuration reduces costs by minimizing the use of external SRAM memory devices. This results in some external memory devices being shared by different types of control blocks, such as flow queue control blocks, frame control blocks and hierarchy control blocks. Both SRAM and DRAM memory devices are used, depending on the content of the control block (Read-Modify-Write or ‘read’ only) at enqueue and dequeue, or Read-Modify-Write solely at dequeue. The scheduler utilizes time-based calendars and weighted fair queueing calendars in the egress calendar design. Control blocks that are accessed infrequently are stored in DRAM memory while those accessed frequently are stored in SRAM.

    摘要翻译： 描述了用于网络流量管理中的流水线配置，用于以分层链接排列的事件的硬件调度。 该配置通过最小化外部SRAM存储器件的使用来降低成本。 这导致一些外部存储器设备被不同类型的控制块共享，例如流队列控制块，帧控制块和层次控制块。 使用SRAM和DRAM存储器件，这取决于控制块的内容（仅读取 - 修改 - 写入或仅读取）在排队和出队，或仅读出 - 修改 - 写出。 调度器在出口日历设计中使用基于时间的日历和加权公平排队日历。 不频繁访问的控制块存储在DRAM存储器中，而频繁访问的控制块存储在SRAM中。

    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position
    98.
    发明授权
    System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
    网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置

    公开(公告)号：US07412546B2

    公开(公告)日：2008-08-12

    申请号：US11320277

    申请日：2005-12-27

    申请人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    发明人： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

    IPC分类号： G06F5/00 ,  G06F15/16

    CPC分类号： H04L49/901 ,  H04L49/103 ,  H04L49/3018 ,  H04L49/90 ,  H04L49/9094

    摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes several control blocks, one for each data buffer, each containing control information linking one buffer to another. Each control block has a last bit feature which is a single bit settable to “one or “zero” and indicates the transmission of when the data buffer having the last bit. The last bit is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit is communicated to the network processor indicating the ending of a particular frame.

    摘要翻译： 提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。 网络处理器包括几个控制块，每个数据缓冲器一个，每个包含将一个缓冲器链接到另一个的控制信息。 每个控制块具有最后一位特征，其是可设置为“一个或”零“的单个位，并且指示何时数据缓冲器具有最后位，当最后一位处于第一位置时，当附加数据缓冲器为 被链接到先前的数据缓冲器，指示要发送附加数据缓冲器，并且当没有附加数据缓冲器被链接到先前的数据缓冲器时的第二位置，最后位的位置被传送到指示结束的网络处理器 的特定框架。

    Method and structure for enqueuing data packets for processing
    99.
    发明授权
    Method and structure for enqueuing data packets for processing 失效
    排队处理数据包的方法和结构

    公开(公告)号：US07406080B2

    公开(公告)日：2008-07-29

    申请号：US10868725

    申请日：2004-06-15

    申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Gordon T. Davis ,  Fabrice J. Verplanken

    IPC分类号： H04L12/56

    CPC分类号： H04L49/90 ,  H04L49/9042 ,  H04L49/9073 ,  H04L69/22

    摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.

    摘要翻译： 提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。 网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。 芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。 该方法包括利用报头信息来识别分组的其余部分的位置和范围。 当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时 有空间。