公开(公告)号：US20150194042A1

公开(公告)日：2015-07-09

申请号：US14589499

申请日：2015-01-05

Applicant: Prolific Technology Inc.

Inventor： Chia-Chang HSU

IPC: G08B21/18 ,  G08B3/10 ,  G08B5/36

CPC classification number: G01R22/10 ,  H01R25/003

Abstract: An electrical energy transferring device coupled to an electrical energy receiving device is provided. The electrical energy transferring device includes an electrical source measuring unit and a power indicating unit. The electrical source measuring unit detects a power consumption and/or a charging status of the electrical energy receiving device. The power indicating unit is coupled to the electrical source measuring unit for showing the power consumption and/or the charging status of the electrical energy receiving device by a color signal and/or an audio signal.

Abstract translation: 提供耦合到电能接收装置的电能转移装置。 电能传递装置包括电源测量单元和电源指示单元。 电源测量单元检测电能接收装置的功率消耗和/或充电状态。 功率指示单元耦合到电源测量单元，用于通过彩色信号和/或音频信号显示电能接收装置的功率消耗和/或充电状态。

公开(公告)号：US08281095B2

公开(公告)日：2012-10-02

申请号：US12707060

申请日：2010-02-17

Applicant: Po-Yuan Chen ,  Jue-Wen Liu

Inventor： Po-Yuan Chen ,  Jue-Wen Liu

IPC: G06F12/00

CPC classification number: G06F11/1466 ,  G06F11/2087

Abstract: A data storage system and the backup method thereof are provided. The data storage system includes a storage device and a storage controller. The storage controller is coupled to the storage device and used for dividing the storage device into a primary data block and a backup data block and setting the data storage system to operate under one of a real time backup mode and a non-real time backup mode. Under the non-real time backup mode, the storage controller backups the data stored in the primary data block to the backup data block when the data storage system is idle.

Abstract translation: 提供了一种数据存储系统及其备份方法。 数据存储系统包括存储设备和存储控制器。 存储控制器耦合到存储设备，用于将存储设备划分成主数据块和备份数据块，并将数据存储系统设置为在实时备份模式和非实时备份模式之一下操作 。 在非实时备份模式下，当数据存储系统空闲时，存储控制器将存储在主数据块中的数据备份到备份数据块。

公开(公告)号：US07906952B2

公开(公告)日：2011-03-15

申请号：US12400809

申请日：2009-03-10

Applicant: Kuo-Jen Kuo ,  Yu-Lung Hung ,  Kang-Shou Chang

Inventor： Kuo-Jen Kuo ,  Yu-Lung Hung ,  Kang-Shou Chang

IPC: G05F1/40

CPC classification number: G05F1/56

Abstract: A voltage regulator includes a comparator, a first voltage output unit, a second voltage output unit, a third voltage output unit, a first switch and a second switch. The voltage regulator receives an operating voltage and a reference voltage generated by a reference voltage generator, and then outputs a corresponding output voltage. The voltage regulator of the present invention can provide an operation mode, a suspend mode and a standby mode and can be switched among these modes to provide corresponding current driving capacity for respective operation states. When in the operation mode, the voltage regulator can supply a great current. When in the suspend mode, the voltage regulator consumes less power. When in the standby mode, the voltage regulator consumes even less power.

Abstract translation: 电压调节器包括比较器，第一电压输出单元，第二电压输出单元，第三电压输出单元，第一开关和第二开关。 电压调节器接收由参考电压发生器产生的工作电压和参考电压，然后输出相应的输出电压。 本发明的电压调节器可以提供操作模式，暂停模式和待机模式，并且可以在这些模式之间切换，以为相应的操作状态提供对应的电流驱动能力。 在运行模式下，电压调节器可以提供较大的电流。 当处于暂停模式时，电压调节器消耗的功率较小。 当处于待机模式时，电压调节器消耗更少的功率。

公开(公告)号：US07725626B2

公开(公告)日：2010-05-25

申请号：US12003745

申请日：2007-12-31

Applicant: Hsin-Chuan Chen ,  Chin-Hsing Chen

Inventor： Hsin-Chuan Chen ,  Chin-Hsing Chen

IPC: G06F13/12

CPC classification number: G06F3/023

Abstract: A multi-media KVM switch is for providing an output signal to drive a user-interface output device. The multi-media KVM switch comprises an embedded multi-media system, an arbiter and a multiplexer. The embedded multi-media system is enabled as receiving an enabling signal and providing a first device signal. The arbiter is for determining an operational state of at least a computer system in response to a second device signal outputted by the at least computer system. The arbiter provides the enabling signal to enable the embedded multi-media system when the at least a computer system is in a standby or an off state, and the arbiter is further for providing a selection signal. The multiplexer is for receiving the first and the second device signals, and outputting one of the first and the second device signals as the output signal to the user-interface output device.

Abstract translation: 多媒体KVM切换器用于提供输出信号来驱动用户界面输出设备。 多媒体KVM切换器包括嵌入式多媒体系统，仲裁器和多路复用器。 嵌入式多媒体系统被启用为接收使能信号并提供第一设备信号。 仲裁器用于响应于由至少计算机系统输出的第二设备信号来确定至少一个计算机系统的操作状态。 当所述至少一个计算机系统处于待机或关闭状态时，所述仲裁器提供使能信号以使得所述嵌入式多媒体系统能够进行，并且所述仲裁器还用于提供选择信号。 复用器用于接收第一和第二设备信号，并将第一和第二设备信号中的一个作为输出信号输出到用户接口输出设备。

公开(公告)号：US07649329B2

公开(公告)日：2010-01-19

申请号：US11752305

申请日：2007-05-23

Applicant: Kuang-Yao Cheng

Inventor： Kuang-Yao Cheng

IPC: H02P6/06

CPC classification number: H02P6/182 ,  H02P6/16

Abstract: A method and a circuit for controlling a motor and a brushless motor using the same are provided. The brushless motor includes three phase coils, wherein the first terminals of all the phase coils are coupled to a common node. The method includes following steps: among the above-mentioned three phase coils, when there is no current flowing through the first phase coil of the above-mentioned three phase coils and a current flows from the second terminal of the second coil to the second terminal of the third phase coil, detecting the voltage at the second terminal of the first phase coil to be a first specific voltage; detecting the voltage drop of a DC sensing resistor to be a second specific voltage; and utilizing the first specific voltage, the second specific voltage and the DC voltage supplied to the motor to estimate zero crossing points for controlling the motor.

Abstract translation: 提供了一种用于控制电动机的方法和电路以及使用其的无刷电动机。 无刷电动机包括三相线圈，其中所有相线圈的第一端子耦合到公共节点。 该方法包括以下步骤：在上述三相线圈中，当没有电流流过上述三相线圈的第一相线圈并且电流从第二线圈的第二端子流到第二端子时 检测第一相线圈的第二端子处的电压为第一特定电压; 检测直流感测电阻器的电压降为第二特定电压; 利用提供给电动机的第一特定电压，第二特定电压和直流电压来估计用于控制电动机的过零点。

公开(公告)号：US07596655B2

公开(公告)日：2009-09-29

申请号：US11368488

申请日：2006-03-07

Applicant: Yu-Hsien Wang ,  Chanson Lin ,  Tung-Hsien Wu ,  Chien-Chang Su ,  Gow-Jeng Lin ,  Ching-Chung Hsu ,  Kuang-Yuan Chen

Inventor： Yu-Hsien Wang ,  Chanson Lin ,  Tung-Hsien Wu ,  Chien-Chang Su ,  Gow-Jeng Lin ,  Ching-Chung Hsu ,  Kuang-Yuan Chen

IPC: G06F12/00

CPC classification number: G06F12/0246

Abstract: A flash storage comprises a flash memory, including a plurality of physical memory blocks, each of physical memory blocks comprising a plurality of memory segments, and a plurality of physical sectors, and each of physical sectors being further provided therein with at least a user data column and a logical address pointer column. When physical data is written into the user data column, writing logical address pointer data into the logical address pointer column of the same physical sector may be performed together by the control of a micro-controller. Furthermore, the logical address pointer data in the same memory segment are arranged to be a backup memory segment address mapping table and then stored in one physical memory block. The backup memory segment address mapping table may be loaded directly and stored into a registered memory by the micro-controller when the system boots. Thus, not only shortening the startup duration of the flash storage, but also saving the memory capacity of the registered memory and securing data access may be obtained.

Abstract translation: 闪存存储器包括闪速存储器，其包括多个物理存储器块，每个物理存储器块包括多个存储器段和多个物理扇区，并且每个物理扇区进一步在其中提供至少一个用户数据 列和逻辑地址指针列。 当将物理数据写入用户数据列时，可以通过微控制器的控制将逻辑地址指针数据写入相同物理扇区的逻辑地址指针列中。 此外，同一存储器段中的逻辑地址指针数据被布置为备份存储器段地址映射表，然后存储在一个物理存储器块中。 备份存储器段地址映射表可以在系统启动时由微控制器直接加载并存储到注册的存储器中。 因此，不仅可以缩短闪存存储器的启动持续时间，还可以节省注册存储器的存储容量并保护数据访问。

公开(公告)号：US07526014B2

公开(公告)日：2009-04-28

申请号：US11007163

申请日：2004-12-09

Applicant: Chia-Chang Hsu

Inventor： Chia-Chang Hsu

IPC: H04B1/69 ,  H04B1/707 ,  H04B1/713

CPC classification number: H04B1/707 ,  G01S19/30 ,  H04B1/709 ,  H04B2201/70715

Abstract: The present invention discloses correlation architecture in the application of full-digital GPS (Global Positioning System) receivers. According to the present invention, a satellite C/A code generator is employed to generate N-bit parallel code data at a time, and a Doppler frequency generator is used to generate N-bit parallel Doppler frequency data at a time. Signals received by the receiver can be temporarily stored in a buffer that provides N-bit parallel reception data to a correlation circuit. In the correlation circuit, a N-bit multiplier is used to multiply the N-bit reception data by the N-bit C/A code data and the N-bit Doppler frequency data to generate multiplication results. The N-bit multiplication results are thereafter summed up in parallel by a digital summator. Accordingly, the correlator of the present invention can improve circuit performance and save the required cost.

Abstract translation: 本发明公开了全数字GPS（全球定位系统）接收机的应用中的相关架构。 根据本发明，一次使用卫星C / A码发生器来产生N位并行码数据，多普勒频率发生器一次用于产生N位并行多普勒频率数据。 由接收机接收到的信号可以临时存储在向相关电路提供N位并行接收数据的缓冲器中。 在相关电路中，使用N位乘法器将N位接收数据乘以N位C / A码数据和N位多普勒频率数据，以产生乘法结果。 然后，N位乘法结果由数字求和器并行并入。 因此，本发明的相关器可以提高电路性能并节省所需的成本。

公开(公告)号：US07466786B2

公开(公告)日：2008-12-16

申请号：US11161955

申请日：2005-08-24

Applicant: Wen-Hwa Chou ,  Yu-Kuo Chen ,  Kuo-Jen Kuo

Inventor： Wen-Hwa Chou ,  Yu-Kuo Chen ,  Kuo-Jen Kuo

IPC: H03D3/24

CPC classification number: H03K5/00006 ,  H03L7/06

Abstract: A rational number frequency multiplier circuit and a method for generating rational number multiple frequency are disclosed. The circuit receives a plurality of input signals having the same frequency and different phase, and outputs at least one multiple frequency signal. The rational number frequency multiplier circuit includes a frequency divider module, for receiving and dividing the input signals to output frequency-divided signals having the same frequency and different phase; a first phase synthesis module and a second phase synthesis module for receiving and synthesizing the frequency-divided and input signals respectively into a plurality of first pulse period signals and second pulse period signals; and an adder for receiving and combining the first pulse period signals and the second pulse period signals into the multiple frequency signal according to the desired multiplication of the frequency.

Abstract translation: 公开了一种有理数倍频电路和一种产生有理数倍频率的方法。 电路接收具有相同频率和不同相位的多个输入信号，并输出至少一个多频信号。 有理数倍频电路包括分频器模块，用于接收和分频输入信号以输出具有相同频率和不同相位的分频信号; 第一相位合成模块和第二相位合成模块，用于分别将分频和输入信号分别接收并合成多个第一脉冲周期信号和第二脉冲周期信号; 以及加法器，用于根据频率的期望乘法接收并组合第一脉冲周期信号和第二脉冲周期信号到多频信号中。

公开(公告)号：US20080238349A1

公开(公告)日：2008-10-02

申请号：US11752305

申请日：2007-05-23

Applicant: Kuang-Yao Cheng

Inventor： Kuang-Yao Cheng

IPC: H02P6/08 ,  H02P7/06 ,  H02P6/18

CPC classification number: H02P6/182 ,  H02P6/16

Abstract: A method and a circuit for controlling a motor and a brushless motor using the same are provided. The brushless motor includes three phase coils, wherein the first terminals of all the phase coils are coupled to a common node. The method includes following steps: among the above-mentioned three phase coils, when there is no current flowing through the first phase coil of the above-mentioned three phase coils and a current flows from the second terminal of the second coil to the second terminal of the third phase coil, detecting the voltage at the second terminal of the first phase coil to be a first specific voltage; detecting the voltage drop of a DC sensing resistor to be a second specific voltage; and utilizing the first specific voltage, the second specific voltage and the DC voltage supplied to the motor to estimate zero crossing points for controlling the motor.

Abstract translation: 提供了一种用于控制电动机的方法和电路以及使用其的无刷电动机。 无刷电动机包括三相线圈，其中所有相线圈的第一端子耦合到公共节点。 该方法包括以下步骤：在上述三相线圈中，当没有电流流过上述三相线圈的第一相线圈并且电流从第二线圈的第二端子流到第二端子时 检测第一相线圈的第二端子处的电压为第一特定电压; 检测直流感测电阻器的电压降为第二特定电压; 利用提供给电动机的第一特定电压，第二特定电压和直流电压来估计用于控制电动机的过零点。

公开(公告)号：US20080170811A1

公开(公告)日：2008-07-17

申请号：US11964050

申请日：2007-12-26

Applicant: Chih-Ho Hsieh ,  Tung-Ho Tsai ,  Chao-Yi Chen

Inventor： Chih-Ho Hsieh ,  Tung-Ho Tsai ,  Chao-Yi Chen

IPC: G06T1/00

CPC classification number: H04N19/587 ,  H04N19/132 ,  H04N19/162 ,  H04N19/172

Abstract: An image capture apparatus is provided. The apparatus includes an image capture, a memory unit, a sampling unit, and an image coder. The image capture captures a plurality of image data. The memory unit is coupled to the image capture and stores the image data output by the image capture. The sampling unit is coupled to the memory unit to sample the stored image data and outputs a sampling image data. The image coder is coupled to the sampling unit to code and compress the sampling image data.

Abstract translation: 提供了一种图像捕获装置。 该装置包括图像捕获，存储单元，采样单元和图像编码器。 图像捕获捕获多个图像数据。 存储单元耦合到图像捕获并存储由图像捕获输出的图像数据。 采样单元耦合到存储器单元以对存储的图像数据进行采样并输出采样图像数据。 图像编码器耦合到采样单元以对采样图像数据进行编码和压缩。