公开(公告)号：US20110202726A1

公开(公告)日：2011-08-18

申请号：US12656709

申请日：2010-02-12

Applicant: Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Andrew Christopher Rose ,  Richard Roy Grisenthwaite

Inventor： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Andrew Christopher Rose ,  Richard Roy Grisenthwaite

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0815 ,  G06F2212/507 ,  Y02D10/13

Abstract: A data processing apparatus for forming a portion of a coherent cache system comprises at least one master device for performing data processing operations, and a cache coupled to the at least one master device and arranged to store data values for access by that at least one master device when performing the data processing operations. Cache coherency circuitry is responsive to a coherency request from another portion of the coherent cache system to cause a coherency action to be taken in respect of at least one data value stored in the cache. Responsive to an indication that the coherency action has resulted in invalidation of that at least one data value in the cache, refetch control circuitry is used to initiate a refetch of that at least one data value into the cache. Such a mechanism causes the refetch of data into the cache to be triggered by the coherency action performed in response to a coherency request from another portion of the coherent cache system, rather than relying on any actions taken by the at least one master device, thereby providing a very flexible and efficient mechanism for reducing cache latency in a coherent cache system.

Abstract translation: 用于形成相干高速缓存系统的一部分的数据处理设备包括用于执行数据处理操作的至少一个主设备和耦合到该至少一个主设备的高速缓存，并且被配置为存储由该至少一个主站访问的数据值 设备执行数据处理操作。 高速缓存一致性电路响应来自相干高速缓存系统的另一部分的一致性请求，以引起关于存储在高速缓存中的至少一个数据值的一致性动作。 响应于一致性动作导致高速缓存中至少一个数据值无效的指示，使用重新读取控制电路来发起将该至少一个数据值重新读取到高速缓存中。 这种机制导致数据重新取入缓存以由响应于来自相干高速缓存系统的另一部分的一致性请求执行的一致性动作来触发，而不是依赖于由至少一个主设备采取的任何动作，从而 提供了一种非常灵活和有效的机制来减少一致的缓存系统中的缓存延迟。

公开(公告)号：US07747825B2

公开(公告)日：2010-06-29

申请号：US12107350

申请日：2008-04-22

Applicant: Jason Frederick Cantin ,  Steven R. Kunkel

Inventor： Jason Frederick Cantin ,  Steven R. Kunkel

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0831 ,  G06F12/0813 ,  G06F2212/507

Abstract: A method, apparatus, and computer program product are disclosed for reducing the number of unnecessarily broadcast local requests to reduce the latency to access data from remote nodes in an SMP computer system. A shared invalid cache coherency protocol state is defined that predicts whether a memory read request to read data in a shared cache line can be satisfied within a local node. When a cache line is in the shared invalid state, a valid copy of the data is predicted to be located in the local node. When a cache line is in the invalid state and not in the shared invalid state, a valid copy of the data is predicted to be located in one of the remote nodes.Memory read requests to read data in a cache line that is not currently in the shared invalid state are broadcast first to remote nodes. Memory read requests to read data in a cache line that is currently in the shared invalid state are broadcast first to a local node, and in response to being unable to satisfy the memory read requests within the local node, the memory read requests are broadcast to the remote nodes.

Abstract translation: 公开了用于减少不必要地广播的本地请求的数量以减少从SMP计算机系统中的远程节点访问数据的等待时间的方法，装置和计算机程序产品。 定义共享的无效高速缓存一致性协议状态，其预测在本地节点内是否可以满足在共享高速缓存行中读取数据的存储器读取请求。 当高速缓存行处于共享无效状态时，预测数据的有效副本位于本地节点中。 当高速缓存行处于无效状态而不处于共享无效状态时，预测数据的有效副本位于远程节点之一中。 在当前处于共享无效状态的缓存行中读取数据的内存读取请求首先被广播到远程节点。 在当前处于共享无效状态的高速缓存行中读取数据的存储器读取请求首先被广播到本地节点，并且响应于不能满足本地节点内的存储器读取请求，存储器读取请求被广播到 远程节点。

公开(公告)号：US07603524B2

公开(公告)日：2009-10-13

申请号：US12042958

申请日：2008-03-05

Applicant: Matthias A. Blumrich ,  Alan G. Gara ,  Valentina Salapura

Inventor： Matthias A. Blumrich ,  Alan G. Gara ,  Valentina Salapura

IPC: G06F12/08 ,  G06F13/00

CPC classification number: G06F12/0831 ,  G06F12/0822 ,  G06F2212/507 ,  Y02D10/13

Abstract: A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filter that processes each snoop cache request and records addresses of the most recent snoop requests for exactly one source. The snoop cache filter uses vector encoding to record the occurrence of snoop requests for a sequence of consecutive cache lines. All addresses of snoop requests are added to the snoop cache unless a received snoop cache request matches an entry present in the associated snoop cache, in which case the snoop request is discarded. Otherwise, the associated snoop cache request is enqueued for forwarding to the single processor. Information from all snoop cache filters assigned to all ports in the snoop filter unit are removed in the case that data corresponding to any one of the memory addresses contained in snoop cache filter is loaded in the cache hierarchy of the processor the snoop cache filter is assigned to.

Abstract translation: 一种用于在多处理器系统中实现与单个处理器相关联的窥探滤波器单元的方法和装置。 监听过滤器单元具有多个端口，每个端口接收来自正好一个专用源的窥探请求。 与每个端口相关联的是一个侦听缓存过滤器，用于处理每个侦听缓存请求，并记录最近一次侦听请求的地址。 监听高速缓存过滤器使用向量编码来记录连续高速缓存行序列的窥探请求的发生。 侦听请求的所有地址都将添加到侦听缓存中，除非接收到的侦听缓存请求与相关侦听缓存中存在的条目匹配，在这种情况下，侦听请求将被丢弃。 否则，相关联的侦听缓存请求被排入队列以转发到单个处理器。 在分配给窥探过滤器单元中的所有端口的所有侦听缓存过滤器中的信息将被删除，因为与侦听高速缓存过滤器中包含的任何一个存储器地址相对应的数据被加载到处理器的高速缓存层次结构中，该侦听缓存过滤器被分配 至。

公开(公告)号：US20090248982A1

公开(公告)日：2009-10-01

申请号：US12250728

申请日：2008-10-14

Applicant: Shinichi IWASAKI

Inventor： Shinichi IWASAKI

IPC: G06F12/00

CPC classification number: G06F12/0884 ,  G06F12/0822 ,  G06F12/0862 ,  G06F2212/507

Abstract: A cache control apparatus determines whether to adopt or not data acquired by a speculative fetch by monitoring a status of the speculative fetch which is a memory fetch request output before it becomes clear whether data requested by a CPU is stored in a cache of the CPU and time period obtained by adding up the time period from when the speculative fetch is output to when the speculative fetch reaches a memory controller and time period from completion of writing of data to a memory which is specified by a data write command that has been issued, before issuance of the speculative fetch, for the same address as that for which the speculative fetch is issued to when a response of the data write command is returned.

Abstract translation: 高速缓存控制装置在清除CPU所请求的数据是否存储在CPU的高速缓存中之前，通过监视作为存储器取出请求输出的推测提取的状态来确定是否采用通过推测获取获得的数据，以及 通过将推测推送输出到推测提取到达存储器控制器的时间段与从写入数据完成到由存储器发出的数据写入命令指定的存储器的时间段相加而获得的时间段， 在发出推测性提取之前，与返回数据写入命令的响应时相同的地址与发出推测性提取的地址相同。

公开(公告)号：US20090198903A1

公开(公告)日：2009-08-06

申请号：US12024170

申请日：2008-02-01

Applicant: RAVI K. ARIMILLI ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

Inventor： RAVI K. ARIMILLI ,  Gheorghe C. Cascaval ,  Balaram Sinharoy ,  William E. Speight ,  Lixin Zhang

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/0822 ,  G06F2212/507 ,  G06F2212/6028

Abstract: In at least one embodiment, a processor detects during execution of program code whether a load instruction within the program code is associated with a hint. In response to detecting that the load instruction is not associated with a hint, the processor retrieves a full cache line of data from the memory hierarchy into the processor in response to the load instruction. In response to detecting that the load instruction is associated with a hint, a processor retrieves a partial cache line of data into the processor from the memory hierarchy in response to the load instruction.

Abstract translation: 在至少一个实施例中，处理器在执行程序代码期间检测程序代码内的加载指令是否与提示相关联。 响应于检测到加载指令不与提示相关联，处理器响应于加载指令从存储器层次结构检索完整的高速缓存行数据到处理器。 响应于检测到加载指令与提示相关联，处理器响应于加载指令从存储器层次结构检索数据的部分高速缓存行到处理器中。

公开(公告)号：US20090150622A1

公开(公告)日：2009-06-11

申请号：US11953255

申请日：2007-12-10

Applicant: James Johnson Allen, JR. ,  Steven Kenneth Jenkins ,  James A. Mossman ,  Michael Raymond Trombley

Inventor： James Johnson Allen, JR. ,  Steven Kenneth Jenkins ,  James A. Mossman ,  Michael Raymond Trombley

IPC: G06F12/00

CPC classification number: G06F12/0806 ,  G06F2212/507

Abstract: A system and method for handling speculative read requests for a memory controller in a computer system are provided. In one example, a method includes the steps of providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a computer system includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold. In another example, a method includes the steps of providing a speculative dispatch time threshold corresponding to a selected percentage of a period of time required to search a cache of the computer system, and intermixing demand reads and speculative reads in accordance with the speculative dispatch time threshold.

Abstract translation: 提供了一种用于处理计算机系统中的存储器控​​制器的推测读请求的系统和方法。 在一个示例中，一种方法包括以下步骤：提供与可推测性地发布的总读数的选定百分比相对应的推测读取阈值，以及根据推测读取阈值混合需求读取和推测性读取。 在另一示例中，计算机系统包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供对应于可以推测地读取总数的所选百分比的推测读取阈值的电路 以及根据推测性读取阈值来混合需求读取和推测性读取的电路。 在另一示例中，一种方法包括以下步骤：提供与搜索计算机系统的高速缓存所需的时间段的选定百分比相对应的推测性调度时间阈值，以及根据投机调度时间混合需求读取和推测读取 阈。

公开(公告)号：US20090089510A1

公开(公告)日：2009-04-02

申请号：US11864363

申请日：2007-09-28

Applicant: William Lee ,  Thomas Benjamin Berg

Inventor： William Lee ,  Thomas Benjamin Berg

IPC: G06F12/00

CPC classification number: G06F12/0828 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0871 ,  G06F2212/507 ,  G06F2212/621 ,  Y02D10/13

Abstract: A cache coherence manager, disposed in a multi-core microprocessor, includes a request unit, an intervention unit, a response unit and an interface unit. The request unit receives coherent requests and selectively issues speculative requests in response. The interface unit selectively forwards the speculative requests to a memory. The interface unit includes at least three tables. Each entry in the first table represents an index to the second table. Each entry in the second table represents an index to the third table. The entry in the first table is allocated when a response to an associated intervention message is stored in the first table but before the speculative request is received by the interface unit. The entry in the second table is allocated when the speculative request is stored in the interface unit. The entry in the third table is allocated when the speculative request is issued to the memory.

Abstract translation: 设置在多核微处理器中的高速缓存一致性管理器包括请求单元，干预单元，响应单元和接口单元。 请求单元接收相干请求并有选择地发出响应的推测请求。 接口单元选择性地将推测请求转发到存储器。 接口单元至少包括三个表。 第一个表中的每个条目表示第二个表的索引。 第二个表中的每个条目表示第三个表的索引。 当对相关干预消息的响应存储在第一表中但在接口单元接收到推测请求之前，分配第一表中的条目。 当推测请求存储在接口单元中时，分配第二个表中的条目。 当向内存发出推测请求时，会分配第三个表中的条目。

公开(公告)号：US20090043966A1

公开(公告)日：2009-02-12

申请号：US12248209

申请日：2008-10-09

Applicant: Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

Inventor： Xiaowei Shen ,  Man Cheuk Ng ,  Aaron Christoph Sawdey

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F12/0804 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/507

Abstract: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

Abstract translation: 在具有存储器层次结构的计算机系统中，当高级缓存将数据拷贝提供给低级缓存时，共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时，如果数据拷贝是非易失性的，则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制，其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问，则使用非易失性拷贝。 此外，低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制，或者根据某种降级策略将数据拷贝从非易失性变为不稳定。

公开(公告)号：US20090006770A1

公开(公告)日：2009-01-01

申请号：US12113262

申请日：2008-05-01

Applicant: Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

Inventor： Matthias A. Blumrich ,  Dong Chen ,  Alan G. Gara ,  Mark E. Giampapa ,  Philip Heidelberger ,  Dirk I. Hoenicke ,  Martin Ohmacht ,  Valentina Salapura ,  Pavlos M. Vranas

IPC: G06F12/08

CPC classification number: G06F12/0822 ,  G06F12/0831 ,  G06F2212/507 ,  Y02D10/13

Abstract: A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports, each port snoop filter implementing one or more parallel operating sub-filter elements that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.

Abstract translation: 一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。 该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。 每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，每个端口窥探滤波器实现一个或多个并行操作子滤波器元件，其适于同时滤除从相应专用存储器接收的窥探请求 写入源并将这些请求的子集转发到其相关联的处理单元。

公开(公告)号：US20080301398A1

公开(公告)日：2008-12-04

申请号：US11757103

申请日：2007-06-01

Applicant: Ohad Falik ,  Ben-Zion Friedman ,  Jack Doweck ,  Eliezer Weissmann ,  James B. Crossland

Inventor： Ohad Falik ,  Ben-Zion Friedman ,  Jack Doweck ,  Eliezer Weissmann ,  James B. Crossland

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/10 ,  G06F12/1027 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/507 ,  G06F2212/65 ,  G06F2212/657 ,  G06F2212/68

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

Abstract translation: 本发明的实施例一般涉及用于线性到物理地址转换的系统，方法和装置，其支持页面属性。 在一些实施例中，系统接收将存储器指针转换为存储器位置的物理存储器地址的指令。 系统可以返回物理内存地址和一个或多个页面属性。 描述和要求保护其他实施例。