Adaptive mechanisms for supplying volatile data copies in multiprocessor systems
    1.
    发明授权
    Adaptive mechanisms for supplying volatile data copies in multiprocessor systems 失效
    用于在多处理器系统中提供易失性数据副本的自适应机制

    公开(公告)号:US07478197B2

    公开(公告)日:2009-01-13

    申请号:US11458192

    申请日:2006-07-18

    IPC分类号: G06F12/00

    摘要: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

    摘要翻译: 在具有存储器层次结构的计算机系统中,当高级缓存将数据拷贝提供给低级缓存时,共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时,如果数据拷贝是非易失性的,则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制,其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问,则使用非易失性拷贝。 此外,低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性变更为非易失性的易失性促进机制,或者根据某种降级策略将数据副本从非易失性变为不稳定。

    ADAPTIVE MECHANISMS AND METHODS FOR SUPPLYING VOLATILE DATA COPIES IN MULTIPROCESSOR SYSTEMS
    2.
    发明申请
    ADAPTIVE MECHANISMS AND METHODS FOR SUPPLYING VOLATILE DATA COPIES IN MULTIPROCESSOR SYSTEMS 失效
    自适应机制和方法供应多处理器系统中的挥发性数据复制

    公开(公告)号:US20080282032A1

    公开(公告)日:2008-11-13

    申请号:US11458192

    申请日:2006-07-18

    IPC分类号: G06F12/00

    摘要: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

    摘要翻译: 在具有存储器层次结构的计算机系统中,当高级缓存将数据拷贝提供给低级缓存时,共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时,如果数据拷贝是非易失性的,则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制,其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问,则使用非易失性拷贝。 此外,低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制,或者根据某种降级策略将数据拷贝从非易失性变为不稳定。

    Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems
    3.
    发明授权
    Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems 有权
    用于在多处理器系统中提供易失性数据副本的自适应机制和方法

    公开(公告)号:US08131938B2

    公开(公告)日:2012-03-06

    申请号:US12248209

    申请日:2008-10-09

    IPC分类号: G06F12/00

    摘要: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

    摘要翻译: 在具有存储器层次结构的计算机系统中,当高级缓存将数据拷贝提供给低级缓存时,共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时,如果数据拷贝是非易失性的,则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制,其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问,则使用非易失性拷贝。 此外,低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制,或者根据某种降级策略将数据拷贝从非易失性变为不稳定。

    Adaptive Mechanisms and Methods for Supplying Volatile Data Copies in Multiprocessor Systems
    4.
    发明申请
    Adaptive Mechanisms and Methods for Supplying Volatile Data Copies in Multiprocessor Systems 有权
    在多处理器系统中提供易失性数据副本的自适应机制和方法

    公开(公告)号:US20090043966A1

    公开(公告)日:2009-02-12

    申请号:US12248209

    申请日:2008-10-09

    IPC分类号: G06F12/08

    摘要: In a computer system with a memory hierarchy, when a high-level cache supplies a data copy to a low-level cache, the shared copy can be either volatile or non-volatile. When the data copy is later replaced from the low-level cache, if the data copy is non-volatile, it needs to be written back to the high-level cache; otherwise it can be simply flushed from the low-level cache. The high-level cache can employ a volatile-prediction mechanism that adaptively determines whether a volatile copy or a non-volatile copy should be supplied when the high-level cache needs to send data to the low-level cache. An exemplary volatile-prediction mechanism suggests use of a non-volatile copy if the cache line has been accessed consecutively by the low-level cache. Further, the low-level cache can employ a volatile-promotion mechanism that adaptively changes a data copy from volatile to non-volatile according to some promotion policy, or changes a data copy from non-volatile to volatile according to some demotion policy.

    摘要翻译: 在具有存储器层次结构的计算机系统中,当高级缓存将数据拷贝提供给低级缓存时,共享副本可以是易失性的或非易失性的。 当数据拷贝稍后从低级缓存中替换时,如果数据拷贝是非易失性的,则需要将其写回高级缓存; 否则可以从低级缓存中简单地刷新。 高级缓存可以采用易失性预测机制,其自动地确定当高级缓存需要向低级缓存发送数据时是否应提供易失性拷贝或非易失性拷贝。 示例性的易失性预测机制建议如果高速缓存行已被低级缓存连续访问,则使用非易失性拷贝。 此外,低级缓存可以使用根据某些促销策略自动地将数据拷贝从易失性地改变为非易失性的易失性促进机制,或者根据某种降级策略将数据拷贝从非易失性变为不稳定。

    CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT
    5.
    发明申请
    CACHE RECONFIGURATION BASED ON RUN-TIME PERFORMANCE DATA OR SOFTWARE HINT 有权
    基于运行时性能数据或软件提示的缓存重新配置

    公开(公告)号:US20110107032A1

    公开(公告)日:2011-05-05

    申请号:US12985726

    申请日:2011-01-06

    IPC分类号: G06F12/08

    摘要: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

    摘要翻译: 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征,并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构,执行实体的预期参考模式,执行实体的类型,执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性,可用于存储数据的高速缓冲存储器的量,高速缓冲存储器的相干粒度,高速缓存存储器的行大小等。

    METHOD AND SYSTEM FOR A SHARING BUFFER
    6.
    发明申请
    METHOD AND SYSTEM FOR A SHARING BUFFER 有权
    共享缓冲器的方法和系统

    公开(公告)号:US20100138571A1

    公开(公告)日:2010-06-03

    申请号:US12623496

    申请日:2009-11-23

    IPC分类号: G06F5/14 G06F9/46

    摘要: A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.

    摘要翻译: 用于共享缓冲区管理的系统,方法和计算机可读制造品。 该系统包括:预测器模块,用于根据交易的历史信息在运行时预测交易的交易数据大小; 以及资源管理模块,用于响应于所述事务的开始,根据预测的事务数据大小来分配所述事务的共享缓冲器资源,以响应所述事务的成功承诺来记录所述事务所占用的实际共享缓冲区大小;以及 更新交易的历史信息。

    Latency-aware thread scheduling in non-uniform cache architecture systems
    7.
    发明授权
    Latency-aware thread scheduling in non-uniform cache architecture systems 有权
    在非均匀缓存架构系统中的延迟感知线程调度

    公开(公告)号:US07574562B2

    公开(公告)日:2009-08-11

    申请号:US11491413

    申请日:2006-07-21

    IPC分类号: G06F12/02

    CPC分类号: G06F12/0842 G06F2212/271

    摘要: A system and method for latency-aware thread scheduling in non-uniform cache architecture are provided. Instructions may be provided to the hardware specifying in which banks to store data. Information as to which banks store which data may also be provided, for example, by the hardware. This information may be used to schedule threads on one or more cores. A selected bank in cache memory may be reserved strictly for selected data.

    摘要翻译: 提供了一种用于在非均匀缓存体系结构中进行延迟识别的线程调度的系统和方法。 可以向硬件提供指令,指定哪些存储体存储数据。 关于哪些银行存储哪些数据的信息也可以由硬件提供。 该信息可用于在一个或多个核心上调度线程。 高速缓冲存储器中的选定存储区可能被严格保留用于所选数据。

    Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache
    8.
    发明授权
    Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache 失效
    至少通过将访问位与高速缓存行相关联并将粒度比特与高级缓存中的高速缓存行相关联的方法,用于至少基于在运行时期内产生的热量分析来重配置缓存存储器

    公开(公告)号:US07467280B2

    公开(公告)日:2008-12-16

    申请号:US11481020

    申请日:2006-07-05

    IPC分类号: G06F12/00

    摘要: A method for reconfiguring a cache memory is provided. The method in one aspect may include analyzing one or more characteristics of an execution entity accessing a cache memory and reconfiguring the cache based on the one or more characteristics analyzed. Examples of analyzed characteristic may include but are not limited to data structure used by the execution entity, expected reference pattern of the execution entity, type of an execution entity, heat and power consumption of an execution entity, etc. Examples of cache attributes that may be reconfigured may include but are not limited to associativity of the cache memory, amount of the cache memory available to store data, coherence granularity of the cache memory, line size of the cache memory, etc.

    摘要翻译: 提供了一种重新配置高速缓冲存储器的方法。 一个方面中的方法可以包括分析访问高速缓冲存储器的执行实体的一个或多个特征,并且基于所分析的一个或多个特征重新配置高速缓存。 分析特性的示例可以包括但不限于执行实体使用的数据结构,执行实体的预期参考模式,执行实体的类型,执行实体的热和功耗。等等 重新配置可以包括但不限于高速缓冲存储器的相关性,可用于存储数据的高速缓冲存储器的量,高速缓冲存储器的相干粒度,高速缓存存储器的行大小等。

    Cache line replacement monitoring and profiling
    9.
    发明授权
    Cache line replacement monitoring and profiling 失效
    缓存线替换监控和分析

    公开(公告)号:US07457926B2

    公开(公告)日:2008-11-25

    申请号:US11131972

    申请日:2005-05-18

    IPC分类号: G06F12/00 G06F13/00 G06F13/28

    摘要: Systems and methods for cache replacement monitoring (CRM) are provided. The system includes a monitored cache comprising a monitored cache line set, the monitored cache line set comprising at least one cache line capable of holding data of a monitored address; and a CRM mechanism operatively associated with the monitored cache. The CRM mechanism collects CRM information for the monitored address. The method includes the steps of collecting CRM information for a monitored address in a monitored cache; and recording the CRM information for the monitored address, when at least one of (1) the monitored address is cached in the monitored cache, (2) the monitored address is replaced in the monitored cache, (3) any cache line in a cache line set corresponding to the monitored address is cached in the monitored cache, and (4) any cache line in a cache line set corresponding to the monitored address is replaced in the monitored cache.

    摘要翻译: 提供了缓存替换监控(CRM)的系统和方法。 所述系统包括被监视的高速缓存,包括被监视的高速缓存行集合,所述监视的高速缓存行集合包括能够保存被监视地址的数据的至少一个高速缓存行; 以及与所监视的缓存可操作地相关联的CRM机制。 CRM机制收集受监控地址的CRM信息。 该方法包括以下步骤:在受监视的高速缓存中收集被监视地址的CRM信息; 以及(1)所监视的地址中的至少一个被缓存在被监视的高速缓存中时,记录所监视的地址的CRM信息,(2)所监视的高速缓存中替换所监视的地址,(3)高速缓存中的任何高速缓存行 对应于被监视地址的线路组被缓存在被监视的高速缓存中,并且(4)在被监视的高速缓存中替换与所监视的地址相对应的高速缓存行集合中的任何高速缓存行。

    Cache line placement prediction for multiprocessor non-uniform cache architecture systems
    10.
    发明授权
    Cache line placement prediction for multiprocessor non-uniform cache architecture systems 失效
    多处理器非均匀缓存架构系统的缓存线放置预测

    公开(公告)号:US07457922B2

    公开(公告)日:2008-11-25

    申请号:US10993784

    申请日:2004-11-20

    申请人: Xiaowei Shen

    发明人: Xiaowei Shen

    IPC分类号: G06F12/00

    摘要: In a multiprocessor non-uniform cache architecture system, multiple CPU cores shares one non-uniform cache that can be partitioned into multiple cache portions with varying access latencies. A placement prediction mechanism predicts whether a cache line should remain in a cache portion or migrate to another cache portion. The prediction mechanism maintains one or more prediction counters for each cache line. A prediction counter can be incremented or decremented by a constant or a variable determined by some runtime information, or set to its maximum or minimum value. An effective placement prediction mechanism can reduce average access latencies without causing cache thrashing among cache portions.

    摘要翻译: 在多处理器非均匀缓存架构系统中,多个CPU内核共享一个不均匀的高速缓存,可以将其分成具有不同访问延迟的多个高速缓存部分。 放置预测机制预测高速缓存行是否应该保留在高速缓存部分中或迁移到另一高速缓存部分。 该预测机制为每个高速缓存行维护一个或多个预测计数器。 预测计数器可以由常数或由某些运行时信息确定的变量递增或递减,或设置为其最大值或最小值。 有效的布局预测机制可以减少平均访问延迟,而不会导致高速缓存部分之间的高速缓存颠簸。