公开(公告)号：US5583812A

公开(公告)日：1996-12-10

申请号：US389295

申请日：1995-02-16

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C11/56 ,  G11C16/04 ,  G11C16/34 ,  G11C29/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/765 ,  G11C29/82 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/7881 ,  H01L29/7885 ,  G11C2211/5613 ,  G11C2211/5631 ,  G11C2211/5634 ,  G11C2211/5644 ,  G11C29/00

摘要： A memory system made up of electrically programmable read only memory (EPROM) or flash electrically erasable and programmable read only memory (EEPROM) cells. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. More than one bit is stored in a cell by establishing more than two distinct threshold states into which the cell is programmed. A series of pulses of increasing voltage is applied to each addressed memory cell during its programming, the state of the cell being read in between pulses. The pulses are terminated upon the addressed cell reaching its desired state or a preset maximum number of pulses has been reached. An intelligent erase algorithm prolongs the useful life of the memory cells. A series of pulses is also applied to a block of cells being erased, the state of at least a sample number of cells being read in between pulses. The erasing process is stopped when the cells being read are determined to have reached a fully erased state or one of a number of other conditions has occurred. Individual records of the number of erase cycles experienced by blocks of flash EEPROM cells are kept, preferable as part of the blocks themselves, in order to maintain an endurance history of the cells within the blocks. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

公开(公告)号：US5546068A

公开(公告)日：1996-08-13

申请号：US362688

申请日：1994-12-22

申请人： Aaron L. Fisher

发明人： Aaron L. Fisher

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C17/00 ,  H01L21/8247 ,  H01L27/115 ,  H03F3/45

CPC分类号： G11C11/56 ,  G11C11/5692 ,  G11C2211/5631 ,  G11C7/06 ,  G11C7/1006

摘要： There is disclosed an integrated circuit including a sense amplifier. The sense amplifier is capable of encoding 2.sup.n levels of output characteristic into a bit pattern of n corresponding bits. The sense amplifier includes a non-zero detect circuit for detecting when the output characteristic is zero. The sense amplifier also includes 2.sup.n -2 comparators for comparing an output characteristic to 2.sup.n -2 reference levels when the output characteristic is non-zero. The 2.sup.n -2 reference levels are constructed from 2.sup.n -2 non-zero levels of the 2.sup.n possible levels of output characteristic. An encoder is coupled to the non-zero detect circuit and the comparators. The encoder encodes the output from the non-zero detect circuit and the outputs from the comparators to corresponding predetermined bit patterns. When the output characteristic is determined to be zero by the non-zero detect circuit, the bit pattern output is a default bit pattern. When the output characteristic is non-zero, the bit pattern takes on predetermined values determined by which pair of reference levels the output falls between, or whether the output characteristic is greater than the largest reference level or less than the smallest reference level.

摘要翻译： 公开了包括读出放大器的集成电路。 读出放大器能够将2n级输出特性编码成n个相应位的位模式。 读出放大器包括用于检测输出特性为零时的非零检测电路。 读出放大器还包括2n-2比较器，用于当输出特性不为零时将输出特性与2n-2个参考电平进行比较。 2n-2个参考电平由输出特性的2n个可能电平的2n-2个非零电平构成。 编码器耦合到非零检测电路和比较器。 编码器将来自非零检测电路的输出和来自比较器的输出编码为对应的预定位模式。 当非零检测电路将输出特性确定为零时，位模式输出是默认位模式。 当输出特性不为零时，位模式取决于输出在输出特性大于最大参考电平或小于最小参考电平之间的参考电平对决定的预定值。

公开(公告)号：US5095344A

公开(公告)日：1992-03-10

申请号：US204175

申请日：1988-06-08

申请人： Eliyahou Harari

发明人： Eliyahou Harari

IPC分类号： G11C17/00 ,  G11C11/56 ,  G11C16/02 ,  G11C16/04 ,  G11C16/34 ,  G11C29/00 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0425 ,  G11C16/349 ,  G11C16/3495 ,  G11C29/765 ,  G11C29/82 ,  H01L27/115 ,  H01L27/11517 ,  H01L29/7881 ,  H01L29/7885 ,  G11C2211/5613 ,  G11C2211/5631 ,  G11C2211/5634 ,  G11C2211/5644 ,  G11C29/00

摘要： Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.