公开(公告)号：US20010034598A1

公开(公告)日：2001-10-25

申请号：US09798595

申请日：2001-03-02

发明人： Gary L. Swoboda

IPC分类号： G06F009/455

CPC分类号： G01R31/31705 ,  G06F9/455 ,  G06F11/261 ,  G06F11/3466 ,  G06F11/3632 ,  G06F11/3636 ,  G06F11/364 ,  G06F11/3648 ,  G06F11/3656 ,  Y02D10/34 ,  Y02T10/82 ,  Y10S370/914

摘要： A scan interface that includes control signals (TRST, TMS, TCK) and data signals (TDI, TDO) normally carried by respective signal paths of the scan interface can be used to carry signals other than signals of the scan interface. A first signal (TMS) and a second signal (TDO) can be time division multiplexed on the signal path that normally carries one of the signals, thereby freeing the signal path that carries the other of the signals to carry a signal other than a signal of the scan interface.

摘要翻译： 包括通常由扫描接口的各个信号路径承载的控制信号（TRST，TMS，TCK）和数据信号（TDI，TDO）的扫描接口可用于承载扫描接口的信号以外的信号。 第一信号（TMS）和第二信号（TDO）可以在通常携带信号之一的信号路径上进行时分复用，从而释放承载另一个信号的信号路径以承载除信号之外的信号 的扫描界面。

公开(公告)号：US6052381A

公开(公告)日：2000-04-18

申请号：US945011

申请日：1998-01-09

申请人： Hans-Jorgen Henriksson ,  Tad Gruber

发明人： Hans-Jorgen Henriksson ,  Tad Gruber

IPC分类号： G06F13/38 ,  H04L25/02 ,  H04J3/22 ,  H04J3/12

CPC分类号： H04L25/0262 ,  G06F13/385 ,  Y10S370/914

摘要： The invention relates to an adapter (10) and a method for a communication card (20), preferably a PCMCIA card, comprising communication electronics by means of a host unit (18) I/O port. The adapter (10) automatically configures the communication card (20) and initiates an automatic connection to a connected host unit with the power supply on, so-called power on. Moreover, it transmits data transparently between the card (20) and the host unit (18) in perceiving changes in data speed and in data format.

摘要翻译： PCT No.PCT / SE97 / 00244 Sec。 371日期1998年1月9日 102（e）日期1998年1月9日PCT 1997年2月14日提交PCT公布。 公开号WO97 / 30396 日期1997年8月21日本发明涉及一种用于通信卡（20）的适配器（10）和方法，优选地是PCMCIA卡，其包括通过主机单元（18）I / O端口的通信电子设备。 适配器（10）自动配置通信卡（20），并在电源接通的情况下启动与连接的主机单元的自动连接，即所谓的通电。 此外，它在卡（20）和主机单元（18）之间透明地传输数据，以感知数据速度和数据格式的变化。

公开(公告)号：US5909434A

公开(公告)日：1999-06-01

申请号：US656652

申请日：1996-05-31

申请人： Joseph P. Odenwalder ,  Brian K. Butler ,  Edward G. Tiedemann, Jr. ,  Ephraim Zehavi

发明人： Joseph P. Odenwalder ,  Brian K. Butler ,  Edward G. Tiedemann, Jr. ,  Ephraim Zehavi

IPC分类号： H04J3/12 ,  H04J3/16 ,  H04J13/00 ,  H04L1/00 ,  H04L1/08 ,  H04L1/12 ,  H04L1/18 ,  H04L25/02 ,  H04L25/05 ,  H04B7/216

CPC分类号： H04L1/0038 ,  H04J3/1688 ,  H04L1/0013 ,  H04L25/0262 ,  H04L25/05 ,  H04L1/0008 ,  H04L1/0071 ,  Y10S370/914

摘要： A novel and improved method and apparatus for generating a constant data rate channel supporting signaling data transmission in an adjustable rate wireless communication system is described. In accordance with one aspect of the invention the rate at which the channel operates may be adjusted based on the particular use and environmental conditions such that the appropriate data rate up to a maximum capability can be achieved. User data is then placed into frames based on the selected rate. When available, signaling data is added into each frames in a predetermined amount. The resulting frame is encoded, repeated and punctured based on the selected rate and whether signaling data has been introduced, and transmitted via RF signals to the receive system. Upon reception, the frame is processed in accordance with having only user data and with having signaling data. That is, the frame is processed both as if it had signaling data and as if no signaling data were present. Once the frame is processed, the particular processing that is more likely to be correct is determined via error checking. If the signaling data processed frame is more likely to have be correct, the signaling data is separated from the user data and each processed accordingly. If the non-signaling data processing is determined to be more likely to be correct, the frame is processed as if it were entirely comprised of user data.

摘要翻译： 描述了一种用于在可调速率无线通信系统中生成支持信令数据传输的恒定数据速率信道的新颖和改进的方法和装置。 根据本发明的一个方面，可以基于具体使用和环境条件来调整信道操作的速率，使得可以实现达到最大能力的适当数据速率。 然后根据所选择的速率将用户数据放入帧中。 如果可用，信令数据以预定的量被添加到每个帧中。 所得到的帧根据所选择的速率进行编码，重复和打孔，并且是否已经引入了信令数据，并且经由RF信号发送到接收系统。 在接收时，根据仅具有用户数据并具有信令数据来处理该帧。 也就是说，帧被处理，就好像它具有信令数据一样，并且好像没有信令数据存在。 一旦帧被处理，更可能正确的特定处理通过错误检查来确定。 如果信令数据处理帧更有可能是正确的，信令数据与用户数据分离，并且相应地进行处理。 如果确定非信令数据处理更可能是正确的，那么该帧被处理好像完全由用户数据组成。

公开(公告)号：US5751741A

公开(公告)日：1998-05-12

申请号：US754768

申请日：1996-11-20

申请人： Raymond Paul Voith ,  Sujit Sudhaman ,  George Hoekstra

发明人： Raymond Paul Voith ,  Sujit Sudhaman ,  George Hoekstra

IPC分类号： H04B7/26 ,  H04L25/05 ,  H03M13/22

CPC分类号： H04B7/2659 ,  H04L25/05 ,  Y10S370/914

摘要： A transceiver (34) includes a rate adaptation buffer (74) that synchronizes a data stream received at a 4.0 kHz rate to a data stream that is transmitted at a 4.05 kHz rate. A transmit section (62) of the transceiver (34) performs rate adaptation using a single rate adaptation buffer. The transmit section (62) includes four autonomous modules which are able to access the data in the rate adaptation buffer (74) independently of one another. These four modules include a CRC-scrambler (72), a FEC encoder (76), an interleaver (78), and a constellation encoder (80). A timing controller (84) prevents contention for accesses to the rate adaptation buffer (74). In addition, each of the four modules perform their respective functions quickly enough to prevent overflow or underflow conditions in the rate adaptation buffer (74). A receive section (64) functions similarly to the transmit section (62).

摘要翻译： 收发器（34）包括速率自适应缓冲器（74），其将以4.0kHz速率接收的数据流与以4.05kHz速率发送的数据流同步。 收发器（34）的发送部分（62）使用单个速率适配缓冲器执行速率自适应。 发送部分（62）包括四个自主模块，它们能够彼此独立地访问速率自适应缓冲器（74）中的数据。 这四个模块包括CRC加扰器（72），FEC编码器（76），交织器（78）和星座编码器（80）。 定时控制器（84）防止对速率适配缓冲器（74）的访问的争用。 此外，四个模块中的每个模块足够快地执行其各自的功能，以防止速率适配缓冲器（74）中的溢出或下溢条件。 接收部分（64）的功能类似于发送部分（62）。

公开(公告)号：US5444704A

公开(公告)日：1995-08-22

申请号：US743661

申请日：1991-08-12

申请人： P. Michael Henderson ,  Edward A. Thoenes

发明人： P. Michael Henderson ,  Edward A. Thoenes

IPC分类号： H04L25/05 ,  H04L29/06 ,  H04M11/06 ,  H04J3/22

CPC分类号： H04L29/06 ,  H04L25/05 ,  H04M11/06 ,  Y10S370/914

摘要： In a multidrop data communication system operating at a first bit rate using the High-Level Data Link Control (HDLC) protocol, dial restoral of communications with a particular tributary at a second, lower bit rate is accomplished without requiring the system as a whole to back down to that lower bit rate. Specifically, the outgoing data is buffered in the dial restoral modem, which discards the data stored in the buffer upon receipt of the HDLC frame which follows any frame in which the so-called "poll" bit is set.

摘要翻译： 在使用高级数据链路控制（HDLC）协议以第一比特率工作的多点数据通信系统中，以第二较低的比特率拨打与特定支路进行通信的恢复，而不需要整个系统 回到那个较低的比特率。 具体来说，输出数据被缓存在拨号盘维修调制解调器中，该拨号调制解调器在接收到设置了所谓的“轮询”位的任何帧之后的HDLC帧的丢弃中存储在缓冲器中的数据。

公开(公告)号：US5418783A

公开(公告)日：1995-05-23

申请号：US992060

申请日：1992-12-17

申请人： Masateru Yamaki ,  Touru Sogabe

发明人： Masateru Yamaki ,  Touru Sogabe

IPC分类号： H04J3/00 ,  H04J3/06 ,  H04J3/12 ,  H04M7/06 ,  H04Q11/04 ,  H04J3/22

CPC分类号： H04J3/0629 ,  H04J3/12 ,  Y10S370/914

摘要： A common channel signal extraction/insertion device for a multiplexed digital transmission system includes a common channel signal insertion/extraction circuit instead of time switches. The common channel signal insertion/extraction circuit includes: a receiver-side speed converter memory 51A for buffering the multiplexed signal 13 received from the multiplexer circuit 3; and a transmitter-side speed converter memory 52A for buffering the common channel signals received from the common channel signal controller 7. The high-speed and the low-speed side reading and writing operations are controlled by the high-speed side controller 51C and the low-speed side controller 51D, respectively. The selector 53 selects between the common channel signals read out from the transmitter-side speed converter memory 52A and the data supplied from the digital switching channel 6, thereby obtaining the multiplexed signal 13a and outputting it to the demultiplexer 12.

摘要翻译： 用于复用数字传输系统的公共信道信号提取/插入装置包括公共信道信号插入/提取电路，而不是时间开关。 公共信道信号插入/提取电路包括：用于缓冲从多路复用器电路3接收的复用信号13的接收机侧速度转换器存储器51A; 以及用于缓冲从公共信道信号控制器7接收的公共信道信号的发送器侧速度转换器存储器52A。高速侧和低速侧读取和写入操作由高速侧控制器51C和 低速侧控制器51D。 选择器53在从发送器侧速度转换器存储器52A读出的公共信道信号和从数字切换通道6提供的数据之间进行选择，从而获得多路复用信号13a并将其输出到解复用器12。

公开(公告)号：US4215245A

公开(公告)日：1980-07-29

申请号：US974375

申请日：1978-12-29

申请人： Jules A. Bellisio

发明人： Jules A. Bellisio

IPC分类号： H04L25/02 ,  H04L25/49 ,  H04L7/02

CPC分类号： H04L25/4906 ,  H04L25/0262 ,  Y10S370/914

摘要： A synchronous digital transmission system (12), operating over a prescribed range of bit rates, is interfaced with subscribers (10, 11) whose data sources and receivers have different bit rates by means of transmitter and receiver interface networks (13, 14). The transmitter interface network (13) comprises means (20, 21, 23, 24) for phase-locking an integral subharmonic f.sub.o /N of a variable frequency oscillator (22) to an input clock signal, f.sub.1, associated with an input data stream, and means (25, 27) for encoding the data stream for operation at a bit rate corresponding to the fundamental frequency, f.sub.o, of the local oscillator (22) and including one code violation at a prescribed rate, f.sub.1 /M, related to the input clock frequency f.sub.1. The receiver interface network (14) includes means (30, 31, 32) for decoding the received signal and for recovering the input data stream and clock signal.

摘要翻译： 在规定的比特率范围内运行的同步数字传输系统（12）与其数据源和接收机借助于发射机和接收机接口网络（13,14）具有不同比特率的用户（10,11）进行接口。 发射机接口网络（13）包括用于将可变频率振荡器（22）的整体次谐波fo / N相位锁定到与输入数据流相关联的输入时钟信号f1的装置（20,21,23,24） 以及用于以与本地振荡器（22）的基频fo对应的比特率进行操作的数据流进行编码的装置（25,27），并且包括与规定速率f1 / M相关的一个代码违例 输入时钟频率f1。 接收机接口网络（14）包括用于对接收到的信号进行解码并用于恢复输入数据流和时钟信号的装置（30,31,32）。

公开(公告)号：US3931472A

公开(公告)日：1976-01-06

申请号：US467656

申请日：1974-05-07

申请人： Walter J. Gill ,  James A. Mellenger

发明人： Walter J. Gill ,  James A. Mellenger

IPC分类号： H04L5/12 ,  H04L25/03 ,  H04L27/20 ,  H04L27/227 ,  H04J3/06

CPC分类号： H04L27/2067 ,  H04L25/03866 ,  H04L27/2275 ,  H04L5/12 ,  Y10S370/914

摘要： A communications system and method for transmitting and receiving two independently timed (asynchronous) binary data signals on a quadriphase carrier. The four phase ambiguity ordinarily resulting from quadriphase transmission and reception is overcome by uniquely identifying one input channel, for example, by slightly increasing the clock rate of the channel. In reception each channel is demodulated and the data rate of each channel is examined to identify the increased clock rate channel. That channel is then returned to its original clock rate.

摘要翻译： 一种用于在四相载波上发送和接收两个独立定时（异步）二进制数据信号的通信系统和方法。 通常通过唯一地识别一个输入通道来克服通常由四相传输和接收产生的四相歧义，例如通过稍微增加信道的时钟速率。 在接收中，解调每个信道，并检查每个信道的数据速率以识别增加的时钟速率信道。 然后，该通道返回到其原始时钟速率。

公开(公告)号：US3823401A

公开(公告)日：1974-07-09

申请号：US29483972

申请日：1972-10-04

申请人： DATA TRANSMISSION CO

发明人： BERG E ,  CHEN F

IPC分类号： H04L5/22 ,  H04J3/00

CPC分类号： H04L5/22 ,  Y10S370/914

摘要： Disclosed is a common carrier type network for the high speed transmission of digital data. Data channels are multiplexed for transmission over a microwave backbone trunk in a synchronous manner and subscriber interconnection is effected at an intermediate multiplex level by a time division switch matrix. Full duplex transmission is by way of two digitally modulated microwave carriers.

摘要翻译： 公开了用于数字数据的高速传输的通用载波型网络。 数据信道被多路复用以通过微波骨干干线以同步方式进行传输，并且用中间复用级别通过时分开关矩阵实现用户互连。 全双工传输是通过两个数字调制的微波载波。