公开(公告)号：US5325319A

公开(公告)日：1994-06-28

申请号：US144423

申请日：1993-11-02

申请人： Tore M. Andre ,  Mansoor F. Khan

发明人： Tore M. Andre ,  Mansoor F. Khan

IPC分类号： G06F7/38 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537 ,  H03H21/00 ,  H04B3/04 ,  G06F15/31

CPC分类号： G06F7/535 ,  H03H21/0012

摘要： Filtering a signal with an adaptive digital filter includes updating the filter by performing an approximate division of a constant number by a variable number in binary form. The variable number represents a magnitude of energy of the signal to be filtered, and consists of a character bit and a plurality of bits which define the absolute value of the number. The variable number is first transformed by substituting with logic zeros any logic ones that have a lower significance than the most significant logic one of the bits. The first transformed number is then further transformed by reading the character bit of the variable number as a character bit and by reading the bits in the digital word in a reversed order. The resulting value is applied to adjust the adaptive digital filter which filters the signal.

摘要翻译： 使用自适应数字滤波器过滤信号包括通过以二进制形式执行常数的近似除数和可变数来更新滤波器。 可变数表示要滤波的信号的能量的大小，并且由字符位和定义数字的绝对值的多个位组成。 首先通过用逻辑零代替具有比最高有效位的逻辑1更低的有效值的逻辑1来变换可变数。 然后通过读取可变数字的字符位作为字符位并通过以相反的顺序读取数字字中的位来进一步变换第一变换的数字。 应用结果值调整对信号进行滤波的自适应数字滤波器。

公开(公告)号：US5206826A

公开(公告)日：1993-04-27

申请号：US787926

申请日：1991-11-06

申请人： Junji Mori ,  Masato Nagamatsu ,  Itaru Yamazaki ,  Yoshihisa Kondo ,  Nobuhiro Ide ,  Takeshi Yoshida

发明人： Junji Mori ,  Masato Nagamatsu ,  Itaru Yamazaki ,  Yoshihisa Kondo ,  Nobuhiro Ide ,  Takeshi Yoshida

IPC分类号： G06F7/537 ,  G06F7/483 ,  G06F7/506 ,  G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/382 ,  G06F2207/5352 ,  G06F7/4873

摘要： A floating-point division cell consisting of partial remainder data register for storing parallel-partial-remainder data or third partial remainder data, divisor data register for storing parallel-divisor data or third divisor data, low-order divisor data generator for receiving the low-order portion of the divisor data and generating low-order divisor data, low-order partial remainder calculator for obtaining low-order multi-divisor data by multiplying the low-order divisor data and a multiple of 2 together and calculating new low-order partial remainder data by subtracting or adding the low-order multi-divisor data from/to the low-order portion of the partial remainder data, high-order divisor data generator for receiving the high-order portion of the divisor data and generating high-order divisor data, and high-order partial remainder calculator for obtaining high-order multi-divisor data by multiplying the high-order divisor data and a multiple of 2 together and calculating new high-order partial remainder data by subtracting or adding the high-order multi-divisor data from/to the high-order portion of the partial remainder data.

摘要翻译： 由部分余数数据寄存器组成的浮点分割单元，用于存储并行余数数据或第三部分余数数据，用于存储并行除数数据或第三除数数据的除数数据寄存器，用于接收低电平的低位除数数据发生器 除数数据的低阶部分和低阶除数数据，低阶部分余数计算器，用于通过将低阶除数数据和2的倍数相乘并计算新的低阶数来获得低阶多因子数据 通过从部分余数数据的低位部分中减去或添加低阶多因子数据的部分余数数据，高阶除数数据发生器，用于接收除数数据的高阶部分， 高阶除数数据和高阶部分余数计算器，用于通过将高阶除数数据和2的倍数相乘在一起来获得高阶多因子数据，并计算新的高除数数据 通过从/部分余数数据的高阶部分中减去或添加高阶多因数数据，来获得h阶部分余数数据。

公开(公告)号：US5047973A

公开(公告)日：1991-09-10

申请号：US343465

申请日：1989-04-26

申请人： Donald E. Steiss ,  Maria B. Hipona ,  Henry M. Darley

发明人： Donald E. Steiss ,  Maria B. Hipona ,  Henry M. Darley

IPC分类号： G06F7/537 ,  G06F7/52 ,  G06F7/53 ,  G06F7/535 ,  G06F7/552 ,  G06F7/57

CPC分类号： G06F7/5324 ,  G06F7/535 ,  G06F7/5525 ,  G06F7/57 ,  G06F2207/382 ,  G06F2207/5355

摘要： Division and square root calculations are performed using an operand routing circuit (16) for receiving an operand N, and operand D and a seed value S and directing the operands and seed value to a multiplier (38). Single multiplier (38) is configured into two arrays for calculating partial products of N and S and D and S. The results of multiplier (38) are transmitted through switching circuitry (20) or registers (48) (50) either to operand routing circuitry (16) or adder (44) depending on a convergence algorithm. The final result is rounded.

公开(公告)号：US4935892A

公开(公告)日：1990-06-19

申请号：US136365

申请日：1987-12-22

申请人： Tamotsu Nishiyama ,  Shigeo Kuninobu

发明人： Tamotsu Nishiyama ,  Shigeo Kuninobu

IPC分类号： G06F7/537 ,  G06F7/48 ,  G06F7/49 ,  G06F7/535

CPC分类号： G06F7/4824 ,  G06F7/5375

摘要： A high speed divider circuit which implements a shift/subtract division method utilizing signed-digital binary expressions for the internal operands includes a quotient determining circuit which determines the quotient digit from the partial remainder, and a pluarlity of arithmetic cells which determine successive quotient digits by subtracting the product of the divisor and the sequential digits from the sequential partial remainders. The arithmetic cells which process the two lowest significant digits, the cells which process the most significant digits, the cells which process the intermediate digits and the cells which determine the initial partial remainder are each specifically tailored to perform their respective functions and thereby result in a divider which requires fewer circuit elements, and is simpler to implement in an integrated circuit.

摘要翻译： 实现使用用于内部操作数的带符号数字二进制表达式的移位/减法分割方法的高速分频器电路包括：商确定电路，其从部分余数确定商数，以及通过以下方式确定连续商数的多项式： 从顺序部分余数中减去除数的乘积和顺序数字。 处理两个最低有效位的算术单元，处理最高有效位的单元，处理中间位的单元和确定初始部分余数的单元被分别专门用于执行其各自的功能，从而导致 除法器，其要求较少的电路元件，并且是简单的在集成电路中实现。

公开(公告)号：US4901267A

公开(公告)日：1990-02-13

申请号：US167802

申请日：1988-03-14

申请人： Mark Birman ,  George K. Chu ,  Fred A. Ware ,  Selfia Halim

发明人： Mark Birman ,  George K. Chu ,  Fred A. Ware ,  Selfia Halim

IPC分类号： G06F7/487 ,  G06F1/12 ,  G06F7/527 ,  G06F7/53 ,  G06F7/535 ,  G06F7/537 ,  G06F7/552 ,  G06F7/57 ,  G06F9/302 ,  G06F9/38

CPC分类号： G06F9/3885 ,  G06F1/12 ,  G06F7/483 ,  G06F7/57 ,  G06F9/30014 ,  G06F2207/382 ,  G06F2207/3884

摘要： The present invention optimizes the number and ratio of cycles required among the divide/square root unit, multiplier unit and ALU. An intermediate latch with its own clock is provided at the output of the multiplier half-array in the intermediate stage to feed back data for a second pass for double-precision numbers. The multiplier can then be adjusted for either two-cycle latency mode (for optimizing double-precision multiplies) or three-cycle latency mode (for optimizing single-precision multiplies). A separate divide clock is used for the divide/square root unit, and is synchronized with the multiplier cycle clock on input and output. This allows the divide time to be optimized so that it requires fewer clock cycles when a longer multiplier clock cycle time is used.

摘要翻译： 本发明优化了除法/平方根单元，乘法器单元和ALU之间所需的周期数和比率。 在中间级的乘法器半阵列的输出处提供具有其自己的时钟的中间锁存器，以反馈用于双精度数字的第二遍的数据。 然后可以针对两周期延迟模式（优化双精度乘法）或三周期延迟模式（用于优化单精度乘数）来调整乘数。 分频/平方根单位使用单独的分频时钟，并与输入和输出的乘法器周期时钟同步。 这样可以优化分频时间，以便在使用较长的乘法器时钟周期时，需要较少的时钟周期。

公开(公告)号：US4873660A

公开(公告)日：1989-10-10

申请号：US66817

申请日：1987-06-25

申请人： Tamotsu Nishiyama ,  Shigeo Kuninobu

发明人： Tamotsu Nishiyama ,  Shigeo Kuninobu

IPC分类号： G06F7/48 ,  G06F7/537

CPC分类号： G06F7/4824 ,  G06F7/5375

摘要： A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operation from an internal operand such as augend (or minuend) and an addend (or subtrahend) for each digit in addition (or subtraction) of signed digit numbers, carried out as an internal arithmetic operation, and determines an intermediate sum (or intermediate difference). In a second step arithmetic operation, the processor obtains a final sum (or difference) for each digit from the intermediate sum (or intermediate difference) obtained in the first step arithmetic operation and an intermediate carry (or intermediate borrow) from a lower order arithmetic operation. The sign of an internal operand is either inverted or the internal operand is converted to 0 in accordance with the value of a control signal and then provided as the internal operand for processing in the first step arithmetic operation. Such sign inversion or conversion of the operand to zero enables the first and second step arithmetic operations to be performed utilizing addition and/or subtraction only.

摘要翻译： 公开了可以紧凑地制造在LSI芯片上的高速运算处理器。 第一步算术运算中的运算处理器从内部操作数（如加法（或minuend））和加数（或减数）中确定用于高位算术运算的中间进位（或中间借位） 作为内部算术运算进行的有符号位数的减法，并确定中间和（或中间差）。 在第二步算术运算中，处理器从第一步运算中获得的中间和（或中间差）和从低阶运算的中间进位（或中间乘法）获得每个数字的最终和（或差） 操作。 内部操作数的符号是​​反转的，或者根据控制信号的值将内部操作数转换为0，然后作为第一步算术运算中的内部操作数进行处理。 这种符号反转或操作数转换为零使得能够仅利用加法和/或减法执行第一和第二步算术运算。

公开(公告)号：US4724529A

公开(公告)日：1988-02-09

申请号：US701556

申请日：1985-02-14

申请人： Suren Irukulla ,  Bimal V. Patel

发明人： Suren Irukulla ,  Bimal V. Patel

IPC分类号： G06F7/537 ,  G06F7/483 ,  G06F7/49 ,  G06F7/493 ,  G06F7/52 ,  G06F7/533 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F7/49 ,  G06F7/4917 ,  G06F7/5375

摘要： A method and apparatus for radix-.beta. non-restoring division. The division process occurs in four phases. In a first phase, the input operands are transformed to produce a divisor lying in a designated numerical range. Next, a transitional phase involves generating an initial radix-.beta. quotient digit from the transformed numerator. An iterative phase of the process generates successive partial remainders according to a recursive method. From the sign and a single radix-.beta. digit of each of these partial remainders, the process generates a radix-.beta. quotient digit. Further, a fourth phase, which may run concurrently with the transitional and iterative phases, involves accumulating successively generated quotient digits to produce a final quotient value.

摘要翻译： 基数β恢复分裂的方法和装置。 分割过程分四个阶段进行。 在第一阶段中，输入操作数被变换以产生位于指定数值范围内的除数。 接下来，过渡阶段涉及从转换的分子生成初始的基数β商数。 该过程的迭代阶段根据递归方法产生连续的部分余数。 从符号和每个这些部分余数的单个基数β数字，该过程生成基数β商数。 此外，可以与过渡和迭代阶段同时运行的第四阶段涉及累积连续生成的商数以产生最终商值。

公开(公告)号：US4718032A

公开(公告)日：1988-01-05

申请号：US701573

申请日：1985-02-14

申请人： Suren Irukulla ,  Bimal V. Patel

发明人： Suren Irukulla ,  Bimal V. Patel

IPC分类号： G06F7/537 ,  G06F1/035 ,  G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F1/0356 ,  G06F2207/5354

摘要： A range transformation method for transforming the normalized divisor in a division calculation to a range wherein the transformed value differs from one by no more than the quantity 2.sup.-n. The method and apparatus generate the transform multiplier value from a first high order "q" digits of the divisor and generate an out-of-range indicator signal from at least those same digits. The thus generated multiplier value is modified in response to the out-of-range indicator signal when an out-of-range condition is indicated. The apparatus employs a read-only-memory for enabling the generation of the transform multiplier value without requiring either large table look-up storage or multiplicative functions. As a result, various division methods requiring an initial transformation to provide a divisor which approaches one in value can be efficiently implemented.

摘要翻译： 一种用于将分割计算中的归一化除数变换到其中变换值与1不同于量2-n的范围的范围变换方法。 该方法和装置从除数的第一高阶“q”位生成变换乘数值，并从至少相同数字生成超范围指示信号。 当指示超出范围条件时，响应于超出范围指示符信号来修改由此产生的乘数值。 该装置采用只读存储器，以便能够生成变换乘数值，而不需要大的表查找存储或乘法函数。 结果，可以有效地实现需要初始变换以提供接近于一个值的除数的各种分割方法。