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1.发明授权
公开(公告)号：US4878192A
公开(公告)日：1989-10-31
申请号：US70565
申请日：1987-07-07
申请人： Tamotsu Nishiyama , Shigeo Kuninobu
发明人： Tamotsu Nishiyama , Shigeo Kuninobu
CPC分类号： G06F7/4824 , G06F7/5375
摘要： An arithmetic processor and an addition/subtraction circuit therefor are disclosed. The arithmetic processor comprises a plurality of the addition/subtraction units arranged in parallel, each unit being capable of carrying out addition (or subtraction) with respect to respective digits of two operands. An addition/subtraction unit comprises a first circuit and a second circuit coupled to receive binary signals each representing a respective digit of the operands. At least a first of the two binary signals is a 2-bit signal representing a signed digit expression, one bit of which ("the sign bit") represents the sign of one of the digits of the operands and the other bit of which ("the magnitude bit") represents the magnitude of that one digit of the operands. The first circuit provides a binary signal representing an intermediate carry (or borrow) and the second circuit provides a binary signal representing an intermediate sum (or difference) from the two binary signals representing the digits of the operands. The addition/subtraction unit further comprises a third circuit which is coupled to receive the intermediate sum (or difference) binary signal output from the second circuit and a binary signal representing an intermediate carry (or borrow) from a next-lower-order digit, and outputs a 2-bit binary signal representing an addend (or subtrahend). That 2-bit signal output by the third circuit represents a signed digit expression, one bit, i.e., the sign bit, represents the sign of the addend (or subtrahend) and the other bit, i.e., the magnitude bit, represents the magnitude of the addend (or subtrahend).
摘要翻译： 公开了一种运算处理器及其加/减电路。 算术处理器包括并行布置的多个加减运算单元，每个单元能够相对于两个操作数的相应数字执行加法（或减法）。 加法/减法单元包括第一电路和第二电路，其耦合以接收每个表示操作数的相应数字的二进制信号。 两个二进制信号中的至少一个是表示有符号数字表达式的2位信号，其中的一位（“符号位”）表示操作数的数字之一的符号， “幅度位”）表示操作数的一位数字的大小。 第一电路提供表示中间进位（或借位）的二进制信号，并且第二电路提供表示来自表示操作数的数字的两个二进制信号的中间和（或差）的二进制信号。 加法/减法单元还包括第三电路，其被耦合以接收从第二电路输出的中间和（或差分）二进制信号和表示来自下一位数字的中间进位（或借位）的二进制信号， 并输出表示加数（或减数）的2位二进制信号。 由第三电路输出的2位信号表示有符号数字表达式，一位，即符号位，表示加数（或减数）的符号，而另一位，即幅度位表示 加数（或减数）。
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公开(公告)号：US4866657A
公开(公告)日：1989-09-12
申请号：US86967
申请日：1987-08-18
CPC分类号： G06F7/4824 , G06F7/5375
摘要： A high speed arithmetic processor and adder circuitry thereof are disclosed in which carry (borrow) propagation is never more than one digit. Addition (or subtraction) are performed by: (a) determining an intermediate carry (or borrow) at the i-th order position and an intermediate sum (or difference) at the i-th order position from the addend (or subtrahend) and the augend (or minuend) and (b) determining the sum (or difference) of the intermediate sum (or difference) at the i-th order position and the intermediate carry (or borrow) at the (i-1)-th or next-lower-order position. Logic equations, truth tables and circuitry are disclosed for implementing several embodiments of the invention.
摘要翻译： 公开了一种高速算术处理器及其加法器电路，其中进位（借位）传播永远不超过一位数。 通过以下方式执行加法（或减法）：（a）确定第i级位置的中间进位（或借位）以及从加数（或减数）和第i级位置的中间和（或差） 加强（或调节）和（b）确定第i-1级位置上的中间总和（或差异）与第（i-1）或 下一级位置。 公开了用于实现本发明的几个实施例的逻辑方程，真值表和电路。
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公开(公告)号：US4866655A
公开(公告)日：1989-09-12
申请号：US74892
申请日：1987-07-17
CPC分类号： G06F7/4824 , G06F7/5375
摘要： An arithmetic processor is disclosed for performing arithmetic operations utilizing an arithmetic operand represented by a signed digit expression having a plurality of digits which may have a positive, zero or negative value. The processor comprises: first circuitry coupled to receive a signal related to the most significant digit of a signed digit expression number Y having nonnegative (or nonpositive) digits other than the most significant digit, and for providing in response to a control signal, a signal representing the logical negation or inversion of the sign of the most significant digit; second circuitry coupled to receive at least one signal related to digits other than the most significant digit of the number Y, and for providing in response to a control signal, at least one signal representing the logical negation or inversion of those digits; and third circuitry coupled to receive a signal related to the least significant digit of the number Y, and for providing in response to a control signal, a signal representing the least significant digit plus 1 (or minus 1). The first and second circuitry invert the signs of the digits of the number Y, and the third circuitry adds (or subtracts) 1 from the least significant digit. The processor also includes circuitry coupled to receive the signals provided by the first, second and third circuitry and a signal representing a number X, and providing a signal representing the sum or difference of the numbers X and Y depending on the control signal.
摘要翻译： 公开了一种算术处理器，用于利用由具有多个可能具有正，零或负值的数字的有符号数字表达式表示的算术运算数进行算术运算。 该处理器包括：第一电路，被耦合以接收与具有除最高有效位之外的非负（或非正））数字的有符号数字表达式数Y的最高有效位相关的信号，并且响应于控制信号提供信号 代表最重要数字的符号的逻辑否定或倒置; 第二电路，被耦合以接收与数字Y以外的数字相关的至少一个信号，并且响应于控制信号提供表示这些数字的逻辑否定或反转的至少一个信号; 以及第三电路，被耦合以接收与数字Y的最低有效位相关的信号，并且响应于控制信号提供表示最低有效数字加上1（或1）的信号。 第一和第二电路反转数字Y的数字的符号，并且第三电路从最低有效数字加1（或减1）。 处理器还包括耦合以接收由第一，第二和第三电路提供的信号的电路，以及表示数字X的信号，并根据控制信号提供表示数字X和Y的和或差的信号。
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4.发明授权
公开(公告)号：US4864528A
公开(公告)日：1989-09-05
申请号：US74971
申请日：1987-07-17
CPC分类号： G06F7/4824 , G06F7/5375
摘要： A high speed processor including a multiplier is disclosed. The multiplier includes a multiplier recorder circuit which may record multipliers in groups of digits, and intermediate partial product generators which generate partial products from the recorded digits and a multiplicand. Addition/subtraction is then carried out on the intermediate partial products generated by the partial product generators. The processor may operate using signed digit expressions.
摘要翻译： 公开了一种包括乘法器的高速处理器。 乘法器包括可记录数字组的乘法器的乘法器记录器电路和从记录的数字和被乘数产生部分乘积的中间部分乘积生成器。 然后对由部分积发生器产生的中间部分积进行加法/减法。 处理器可以使用带符号数字表达式操作。
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公开(公告)号：US5031136A
公开(公告)日：1991-07-09
申请号：US239243
申请日：1990-05-07
申请人： Tamotsu Nishiyama , Shigeo Kuninobu
发明人： Tamotsu Nishiyama , Shigeo Kuninobu
CPC分类号： G06F7/544 , G06F7/4824 , G06F7/523 , G06F7/5338 , G06F7/5375
摘要： A high speed arithmetic processor includes an array of arithmetic cells which operate on digits internally represented in a signed-digit binary format. Certain of these cells perform subtraction operations on two ordinary binary digits, and produce the difference in a 2-bit signed-digit binary format, without requiring a separate ordinary binary to signed-digit binary converter.
摘要翻译： 一个高速运算处理器包括一个运算数组的运算单元，这些运算单元以一个有符号位二进制格式内部表示的数字运算。 这些小区中的某些小区对两个普通二进制数字执行减法运算，并产生2位有符号数位二进制格式的差异，而不需要单独的普通二进制到有符号位二进制转换器。
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公开(公告)号：US4868777A
公开(公告)日：1989-09-19
申请号：US95525
申请日：1987-09-10
CPC分类号： G06F7/544 , G06F7/4824 , G06F7/523 , G06F7/5375
摘要： An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.
摘要翻译： 描述了以高速执行连续相乘操作的运算处理器电缆，其中内部表示为进位保存或有符号数字表达式的结果乘积可以以该形式直接输入作为下一个连续乘法运算的乘数。 此外，提供了一个乘法器重新编码器电路，其以进位保存或有符号位表达式的形式将二进制乘法器重新编码为基数4的有符号数字，以进一步提高操作速度。
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公开(公告)号：US4935892A
公开(公告)日：1990-06-19
申请号：US136365
申请日：1987-12-22
申请人： Tamotsu Nishiyama , Shigeo Kuninobu
发明人： Tamotsu Nishiyama , Shigeo Kuninobu
CPC分类号： G06F7/4824 , G06F7/5375
摘要： A high speed divider circuit which implements a shift/subtract division method utilizing signed-digital binary expressions for the internal operands includes a quotient determining circuit which determines the quotient digit from the partial remainder, and a pluarlity of arithmetic cells which determine successive quotient digits by subtracting the product of the divisor and the sequential digits from the sequential partial remainders. The arithmetic cells which process the two lowest significant digits, the cells which process the most significant digits, the cells which process the intermediate digits and the cells which determine the initial partial remainder are each specifically tailored to perform their respective functions and thereby result in a divider which requires fewer circuit elements, and is simpler to implement in an integrated circuit.
摘要翻译： 实现使用用于内部操作数的带符号数字二进制表达式的移位/减法分割方法的高速分频器电路包括：商确定电路，其从部分余数确定商数，以及通过以下方式确定连续商数的多项式： 从顺序部分余数中减去除数的乘积和顺序数字。 处理两个最低有效位的算术单元，处理最高有效位的单元，处理中间位的单元和确定初始部分余数的单元被分别专门用于执行其各自的功能，从而导致 除法器，其要求较少的电路元件，并且是简单的在集成电路中实现。
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公开(公告)号：US4873660A
公开(公告)日：1989-10-10
申请号：US66817
申请日：1987-06-25
申请人： Tamotsu Nishiyama , Shigeo Kuninobu
发明人： Tamotsu Nishiyama , Shigeo Kuninobu
CPC分类号： G06F7/4824 , G06F7/5375
摘要： A high speed arithmetic processor which may compactly be fabricated on an LSI chip is disclosed. The arithmetic processor in a first-step arithmetic operation determines an intermediate carry (or intermediate borrow) for a higher order arithmetic operation from an internal operand such as augend (or minuend) and an addend (or subtrahend) for each digit in addition (or subtraction) of signed digit numbers, carried out as an internal arithmetic operation, and determines an intermediate sum (or intermediate difference). In a second step arithmetic operation, the processor obtains a final sum (or difference) for each digit from the intermediate sum (or intermediate difference) obtained in the first step arithmetic operation and an intermediate carry (or intermediate borrow) from a lower order arithmetic operation. The sign of an internal operand is either inverted or the internal operand is converted to 0 in accordance with the value of a control signal and then provided as the internal operand for processing in the first step arithmetic operation. Such sign inversion or conversion of the operand to zero enables the first and second step arithmetic operations to be performed utilizing addition and/or subtraction only.
摘要翻译： 公开了可以紧凑地制造在LSI芯片上的高速运算处理器。 第一步算术运算中的运算处理器从内部操作数（如加法（或minuend））和加数（或减数）中确定用于高位算术运算的中间进位（或中间借位） 作为内部算术运算进行的有符号位数的减法，并确定中间和（或中间差）。 在第二步算术运算中，处理器从第一步运算中获得的中间和（或中间差）和从低阶运算的中间进位（或中间乘法）获得每个数字的最终和（或差） 操作。 内部操作数的符号是反转的，或者根据控制信号的值将内部操作数转换为0，然后作为第一步算术运算中的内部操作数进行处理。 这种符号反转或操作数转换为零使得能够仅利用加法和/或减法执行第一和第二步算术运算。
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公开(公告)号：US4085499A
公开(公告)日：1978-04-25
申请号：US754261
申请日：1976-12-27
申请人： Shigeo Kuninobu , Takeshi Ishihara
发明人： Shigeo Kuninobu , Takeshi Ishihara
IPC分类号： H01L21/225 , H01L21/285 , H01L21/321 , B01J17/00
CPC分类号： H01L21/2257 , H01L21/28525 , H01L21/32105 , Y10S148/136 , Y10S438/965
摘要： A method of making an MOS-type semiconductor device wherein the surface thereon for the conductors is flat. For this purpose, a polycrystalline silicon layer is provided and a part of the layer is selectively oxidized, so that the remaining portion of the layer acts as a lead for connecting a functional region such as a source region, a drain region etc. with the conductor layer. When said oxidization is performed, the diffusion from the polycrystalline silicon layer into the substrate occurs due to heating, so that said functional regions are formed at the same time.
摘要翻译： 制造MOS型半导体器件的方法，其中用于导体的表面是平坦的。 为此，提供了多晶硅层，并且该层的一部分被选择性地氧化，使得该层的剩余部分用作将源极区域，漏极区域等功能区域与 导体层。 当进行所述氧化时，由于加热而发生从多晶硅层到基板的扩散，使得所述功能区域同时形成。
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公开(公告)号：US4750026A
公开(公告)日：1988-06-07
申请号：US799556
申请日：1985-11-19
申请人： Shigeo Kuninobu , Eisuke Ichinohe
发明人： Shigeo Kuninobu , Eisuke Ichinohe
IPC分类号： H01L21/822 , H01L21/82 , H01L23/528 , H01L27/04 , H01L27/092 , H01L27/118 , H01L27/02
CPC分类号： H01L23/528 , H01L27/092 , H01L27/11807 , H01L2924/0002 , Y10S257/923
摘要： In a C MOS IC as shown in FIG. 7(A) and FIG. 8, the IC comprises vertical row of horizontally long blocks, each block comprising p-type MOS transistor region and n-type MOS transistor region, the IC comprises horizontal wirings of aluminum (31, 32, 33) and vertical wirings of polycrystalline silicon (61, 62, 63, 64, 65, 41, 42), with insulation films on the upper side and on the lower side of the polycrystalline silicon film, between the rows (I, II, . . .), said horizontal aluminum wirings (31, 32, 33) and said polycrystalline silicon wiring (61, 62 . . ., 41, 42) being appropriately connected through openings (105, 105 . . .) formed in said insulation film inbetween, said vertical polycrystalline silicon wirings being connected through aluminum wirings in said blocks.
摘要翻译： 在如图1所示的C MOS IC中。 图7（A） 如图8所示，IC包括垂直排的水平长块，每个块包括p型MOS晶体管区域和n型MOS晶体管区域，IC包括铝（31,32,33）的水平布线和多晶硅的垂直布线 61,22,63,64,65,41,42），在多层硅膜的上侧和下侧上具有在行（I，II ...）之间的绝缘膜，所述水平铝布线 （31,32,33），并且所述多晶硅布线（61,62 ...，41,42）通过形成在所述绝缘膜之间的开口（105,105 ...）适当地连接，所述垂直多晶硅布线是 通过所述块中的铝布线连接。
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