公开(公告)号：US08588406B2

公开(公告)日：2013-11-19

申请号：US11523773

申请日：2006-09-18

Applicant: Andrew Dellow ,  Rodrigo Cordero

Inventor： Andrew Dellow ,  Rodrigo Cordero

IPC: H04K1/00

CPC classification number: H04L9/0662 ,  H04L2209/04 ,  H04L2209/12

Abstract: A portion of data is obfuscated by performing a bitwise XOR function between bits of the data portion and bits of a mask. The mask is generated based on the memory address of the data portion. A bitfield representing the memory address of the data portion is split into subset bitfields. Each subset then forms the input of a corresponding primary randomizing unit. Each primary randomizing unit is arranged to generate an output bitfield that appears to be randomly correlated with the input, but which may be determined from the input if certain secret information is known. The output of the primary randomizing units is input into a series of secondary randomizing units. Each secondary randomizing unit is arranged to input at least one bit of the output of every primary randomizing unit. The output of the secondary randomizing units are then combined by concatenation to form a data mask.

Abstract translation: 通过在数据部分的位和掩码的位之间执行按位XOR功能来模糊数据的一部分。 基于数据部分的存储器地址生成掩码。 表示数据部分的存储器地址的位字段被分割成子字段。 然后，每个子集形成对应的主随机化单元的输入。 每个主随机化单元被安排成产生似乎与输入随机相关的输出位域，但是如果某些秘密信息是已知的，则可以从输入确定输出位域。 主随机化单元的输出被输入到一系列二次随机化单元中。 每个二次随机化单元被布置成输入每个主随机化单元的输出的至少一位。 然后通过级联组合二次随机化单元的输出以形成数据掩码。

公开(公告)号：US20120263297A1

公开(公告)日：2012-10-18

申请号：US13535162

申请日：2012-06-27

Applicant: Peter Bennett ,  Paul Elliott ,  Andrew Dellow

Inventor： Peter Bennett ,  Paul Elliott ,  Andrew Dellow

IPC: H04N7/167

CPC classification number: H04N21/44 ,  H04N7/165 ,  H04N21/26606 ,  H04N21/42623 ,  H04N21/6334

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals that includes an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. The semiconductor integrated circuit is provided with some functionality restricted in some way by preventing one or more hardware circuit elements from operating, such as an MPEG decoder, display engine, IO ports or main CPU. To enable the functionality, a subscriber must pay for a service and then receives an encrypted message broadcast to the semiconductor integrated circuit that is decrypted and instructs functionality to be turned on or off.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 半导体集成电路具有通过防止一个或多个硬件电路元件操作（例如MPEG解码器，显示引擎，IO端口或主CPU）以某种方式受到限制的某些功能。 为了实现该功能，用户必须支付服务费用，然后接收加密的消息广播到被解密的半导体集成电路，并指示功能被打开或关闭。

公开(公告)号：US08223967B2

公开(公告)日：2012-07-17

申请号：US10575650

申请日：2003-10-16

Applicant: Peter Bennett ,  Paul Elliott ,  Andrew Dellow

Inventor： Peter Bennett ,  Paul Elliott ,  Andrew Dellow

IPC: H04N7/167

CPC classification number: H04N21/44 ,  H04N7/165 ,  H04N21/26606 ,  H04N21/42623 ,  H04N21/6334

Abstract: A semiconductor integrated circuit for the processing of conditional access television signals that includes an input interface for receiving encrypted television signals and an output interface for output of decrypted television signals. The semiconductor integrated circuit is provided with some functionality restricted in some way by preventing one or more hardware circuit elements from operating, such as an MPEG decoder, display engine, IO ports or main CPU. To enable the functionality, a subscriber must pay for a service and then receives an encrypted message broadcast to the semiconductor integrated circuit that is decrypted and instructs functionality to be turned on or off.

Abstract translation: 一种用于处理条件接收电视信号的半导体集成电路，包括用于接收加密的电视信号的输入接口和用于输出解密的电视信号的输出接口。 半导体集成电路具有通过防止一个或多个硬件电路元件操作（例如MPEG解码器，显示引擎，IO端口或主CPU）以某种方式受到限制的某些功能。 为了实现该功能，用户必须支付服务费用，然后接收加密的消息广播到被解密的半导体集成电路，并指示功能被打开或关闭。

公开(公告)号：US08032910B2

公开(公告)日：2011-10-04

申请号：US12778413

申请日：2010-05-12

Applicant: David Lewis ,  Howard Gurney

Inventor： David Lewis ,  Howard Gurney

IPC: H04N7/20 ,  H04N5/932 ,  H04N5/935

CPC classification number: H04N21/4383 ,  H04N21/42646 ,  H04N21/42661 ,  H04N21/42669 ,  H04N21/42692 ,  H04N21/434 ,  H04N21/44004

Abstract: A system comprising first input means for receiving a transport stream from an external source, second input means for receiving an input from a memory, means for connecting the first and second input means to an interface which is arranged to provide an output stream to a decoder. The second input means is arranged to provide an output to the interface in such a form that the interface does not distinguish between the output from the first and second input means.

Abstract translation: 一种系统，包括用于从外部源接收传输流的第一输入装置，用于从存储器接收输入的第二输入装置，用于将第一和第二输入装置连接到被配置为向解码器提供输出流的接口的装置 。 第二输入装置被布置成以这样的形式向接口提供输出，使得接口不区分来自第一和第二输入装置的输出。

公开(公告)号：US20100327913A1

公开(公告)日：2010-12-30

申请号：US12822881

申请日：2010-06-24

Applicant: Mark Trimmer

Inventor： Mark Trimmer

IPC: H03K5/19

CPC classification number: H03K5/19 ,  G06F1/14 ,  H03K5/26

Abstract: There is provided a circuit and method for detecting a bad clock condition on a clock signal that includes sampling the value of the clock signal at a first plurality of time delays following a rising edge on the clock signal. This method also includes sampling the value of the clock signal at a second plurality of time delays following a falling edge on the clock signal.

Abstract translation: 提供了一种用于检测时钟信号上的不良时钟状况的电路和方法，该时钟信号包括在时钟信号的上升沿之后的第一多个时间延迟上对时钟信号的值进行采样。 该方法还包括在时钟信号的下降沿之后的第二多个时间延迟中对时钟信号的值进行采样。

公开(公告)号：US07730508B2

公开(公告)日：2010-06-01

申请号：US10380924

申请日：2001-09-19

Applicant: Steven Haydock

Inventor： Steven Haydock

IPC: H04N7/10

CPC classification number: H04N21/235 ,  H04N21/434 ,  H04N21/435

Abstract: A data transport device for transporting a data stream, the device including: a data stream processing unit for receiving an input data stream including a plurality of data items, performing processing in dependence on the content of the items and forming an output data stream including at least some of the data items; and a data item injection unit including a memory for storing a plurality of injection data items and associated with each injection data item an injection action, and an injection processor arranged to retrieve the injection action for each of the injection data items in turn and in dependence on the retrieved injection action to inject the associated injection data item into the output data stream.

Abstract translation: 一种用于传送数据流的数据传输装置，该装置包括：数据流处理单元，用于接收包括多个数据项的输入数据流，根据项目的内容执行处理，并形成包括在 最少的一些数据项; 以及数据项目注入单元，其包括用于存储多个注射数据项并且与每个注射数据项相关联的注射动作的存储器，以及喷射处理器，其被配置为依次检索每个注射数据项的注射动作 在检索到的注入动作上将相关联的注入数据项注入到输出数据流中。

公开(公告)号：US07545896B2

公开(公告)日：2009-06-09

申请号：US11137105

申请日：2005-05-24

Applicant: Matthew Peter Hutson

Inventor： Matthew Peter Hutson

IPC: H04L7/00

CPC classification number: H04L7/02

Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.

Abstract translation: 一种用于控制第一时钟域中的信号序列向多个其它时钟域的传送的系统。 该系统包括：检测电路，用于检测来自时钟域的信号的接收，并且当从时钟域接收的所有信号具有共同的状态时，设置更新信号; 以及用于接收更新信号的选通电路，并且当更新信号被设置时可操作以允许序列中的下一个信号在第一电路的输入处被接收。

公开(公告)号：US07489724B2

公开(公告)日：2009-02-10

申请号：US10247263

申请日：2002-09-18

Applicant: Robert Geoffrey Warren

Inventor： Robert Geoffrey Warren

IPC: H04B1/38

CPC classification number: G01R31/318552 ,  G01R31/31937

Abstract: A system for controlling communications between a host and a target, the system having a data input for receiving a data signal, a clock input for receiving a clock signal, an oversampling circuit for sampling a received data signal and generating a control signal to control processing of the received data signal based at least in part on samples of the received data signal.

Abstract translation: 一种用于控制主机和目标之间的通信的系统，具有用于接收数据信号的数据输入的系统，用于接收时钟信号的时钟输入，用于对接收的数据信号进行采样的过采样电路，并产生控制信号以控制处理 至少部分地基于所接收的数据信号的样本。

公开(公告)号：US07480783B2

公开(公告)日：2009-01-20

申请号：US10922242

申请日：2004-08-19

Applicant: Mark O. Homewood ,  Paolo Faraboschi

Inventor： Mark O. Homewood ,  Paolo Faraboschi

IPC: G06F12/00 ,  G06F9/26 ,  G06F9/34

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/30145 ,  G06F12/04

Abstract: Disclosed are systems for loading an unaligned word from a specified unaligned word address in a memory, the unaligned word comprising a plurality of indexed portions crossing a word boundry, a method of operating the system comprising: loading a first aligned word commencing at an aligned word address rounded from the specified unaligned word address; identifying an index representing the location of the unaligned word address relative to the aligned word address; loading a second aligned word commencing at an aligned word address rounded from a second unaligned word address; and combining indexed portions of the first and second alinged words using the indentified index to construct the unaligned word.

Abstract translation: 公开了一种用于从存储器中的指定的未对齐字地址加载未对齐字的系统，所述未对齐字包括跨越字边界的多个索引部分，操作所述系统的方法包括：加载从对齐字开始的第一对准字 指定的未对齐字地址四舍五入的地址; 识别表示未对齐字地址相对于对齐字地址的位置的索引; 加载从第二未对齐字地址四舍五入的对齐字地址开始的第二对齐字; 并且使用所述识别的索引来组合所述第一和第二调用字的索引部分以构造所述未对齐字。

公开(公告)号：US20080209106A1

公开(公告)日：2008-08-28

申请号：US11592735

申请日：2006-11-03

Applicant: Peter Bennett ,  Andrew Dellow ,  Jonathan Smailes

Inventor： Peter Bennett ,  Andrew Dellow ,  Jonathan Smailes

IPC: G06F12/02 ,  G06F15/177 ,  G06F12/00

CPC classification number: G06F13/1631 ,  G11C16/08

Abstract: A memory access system including a memory in which data is organized in pages, each page holding a sequence of data elements; means for receiving a requested address including a requested page address and a requested data element address; logic for accessing a current page from the memory using a current page address; logic for reading out data elements of the current page in the sequence in which they are held in memory; logic for comparing the requested page address with the current page address and for issuing a memory access request with the requested page address when they are not the same; and logic operable when the requested page address is the same as the current page address for comparing a requested data element address with the current address of a data element being read out and returning the data element when the requested data element address matches the current data element address.

Abstract translation: 一种存储器访问系统，包括其中以页面组织数据的存储器，每个页面保存数据元素序列; 用于接收包括请求的页面地址和所请求的数据元素地址的所请求的地址的装置; 使用当前页面地址从存储器访问当前页面的逻辑; 用于以它们被保存在存储器中的顺序读出当前页面的数据元素的逻辑; 用于将请求的页面地址与当前页面地址进行比较并用于当它们不相同时发出具有所请求的页面地址的存储器访问请求的逻辑; 以及当所请求的页面地址与当前页面地址相同时可操作的逻辑，用于将所请求的数据元素地址与正被读出的数据元素的当前地址进行比较，并且当所请求的数据元素地址与当前数据元素匹配时返回数据元素 地址。