公开(公告)号：US06694380B1

公开(公告)日：2004-02-17

申请号：US09473271

申请日：1999-12-27

申请人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F1300

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： A processor is disclosed that can map a request from a central processing unit that uses memory-mapped input-output space to a second processing domain, such as a multithreaded processing domain. A request addressed to the input-output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain. The command is executed in the multithreaded processing domain. Information is accessed according to the request in response to executing the command.

摘要翻译： 公开了一种处理器，其可以将来自使用存储器映射的输入 - 输出空间的中央处理单元的请求映射到诸如多线程处理域的第二处理域。 将寻址到中央处理单元的输入 - 输出空间的请求转换为模拟多线程处理域中的组件之间的操作的相应命令。 该命令在多线程处理域中执行。 响应于执行命令，根据请求访问信息。

公开(公告)号：US06643836B2

公开(公告)日：2003-11-04

申请号：US09941923

申请日：2001-08-29

申请人： William R. Wheeler ,  Matthew J. Adiletta

发明人： William R. Wheeler ,  Matthew J. Adiletta

IPC分类号： G06F1750

CPC分类号： G06F17/5022 ,  G06F17/5045

摘要： Displaying information relating to a logic design includes generating a first display that relates to the logic design, the first display being associated with other information not included in the first display, retrieving the other information in response to a user input, and generating a second display that relates to the logic design based on the other information.

公开(公告)号：US06295546B1

公开(公告)日：2001-09-25

申请号：US09223494

申请日：1998-12-31

申请人： Matthew J. Adiletta

发明人： Matthew J. Adiletta

IPC分类号： G06F1500

CPC分类号： H04N19/423 ,  H04N19/126 ,  H04N19/14 ,  H04N19/149 ,  H04N19/15 ,  H04N19/152 ,  H04N19/159 ,  H04N19/169 ,  H04N19/176 ,  H04N19/177 ,  H04N19/192 ,  H04N19/42 ,  H04N19/61

摘要： A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and appatatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system. The double buffer memory locations are chosen so that the intermediate storage register address are orthogonal to the initial source addresses, thereby using one of the properties of the Discrete Cosine Transform to improve speed of operation and reduce the circuit area and system cost.

摘要翻译： 提出了一种使用独特的操作数分解技术结合创新的数据分散和检索过程进行视频图像压缩的方法和装置。 这种特征的组合允许使用通常使用多端口RAMS的单端口RAM结构，例如在相同时间周期中检索两个操作数时。 如应用于离散余弦变换，该方法和appatatus另外允许消除通常的现有技术使用单独的转置矩阵缓冲器。 通过将转置矩阵中间结果存储器存储器与用于另一中间结果的存储器缓冲器组合在双缓冲器系统中来实现单独的转置矩阵缓冲器的消除。 选择双缓冲存储器位置，使得中间存储寄存器地址与初始源地址正交，从而使用离散余弦变换的特性之一来提高操作速度并减少电路面积和系统成本。

公开(公告)号：US6052706A

公开(公告)日：2000-04-18

申请号：US977732

申请日：1997-11-25

申请人： William R. Wheeler ,  Matthew J. Adiletta

发明人： William R. Wheeler ,  Matthew J. Adiletta

IPC分类号： G06F7/52

CPC分类号： G06F7/5324 ,  G06F7/5338 ,  G06F7/535 ,  G06F2207/3884 ,  G06F2207/5352

摘要： In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a succeeding stage. At least one of the pipeline stages includes a means for recirculating an output from the pipeline stage as an input to the pipeline stage for a predetermined number of times before passing the output to a succeeding stage. The predetermined number of times represents a clock period that includes more than one assertion of a clock signal. With such an arrangement, a circuit which performs a process, such as multiplication and division, in accordance with a particular bandwidth requirement requires less hardware than in other circuits performing the same process. The foregoing arrangement provides a flexible approach which can be adapted for particular bandwidth requirements and constraints which vary with each particular application and system in which such a process is performed.

摘要翻译： 根据本发明，提供了一种用于对数据流执行迭代处理的电路。 迭代过程包括对数据流的一部分进行操作以产生作为后级的输入的输出的流水线级。 流水线级中的至少一个包括用于在将输出传递到后级之前将来自流水线级的输出作为输入再循环到流水线级预定次数的装置。 预定次数表示包括多于一个时钟信号的断言的时钟周期。 通过这样的布置，根据特定带宽要求执行诸如乘法和除法的处理的电路比执行相同处理的其它电路中需要的硬件要少。 上述布置提供了一种灵活的方法，该方法可以针对特定的带宽要求和约束进行调整，每个特定的应用和系统在执行这种处理的每一个特定的应用和系统中

公开(公告)号：US5146421A

公开(公告)日：1992-09-08

申请号：US373083

申请日：1989-06-28

申请人： Matthew J. Adiletta ,  Stephen C. Root

发明人： Matthew J. Adiletta ,  Stephen C. Root

IPC分类号： G06F7/53 ,  G06F7/508 ,  G06F7/52

CPC分类号： G06F7/5318

摘要： The binary multiplier circuit for obtaining a product of an M-bit multiplier and an N-bit multiplicand includes a multiplier circuit which produces a matrix of original summand bits having M rows and M+N columns and a matrix reduction circuit. In the matrix reduction circuit, for every column of the matrix having three or more original summand bits, groups of three bits are input into full adder circuits which output a sum bit for that column and a carry bit for the column in the next most significant bit position. For every column having three or fewer original summand bits, and having the least significant column position that is not yet reduced to two or fewer bits, groups of two bits are input into a half adder circuit which outputs a sum bit for that column and carry bit for a column in the next most significant bit position. Iterative reductions are performed for each column by using full adder circuits for every group of three bits in a column and by using a half adder circuit for any remaining group of two bits in a column. The reduction continues until each column of the matrix is reduced to two or fewer bits. The remaining two rows of bits can be input to a two-stage carry-propagating adder circuit to output a sum equal to the product.

摘要翻译： 用于获得M位乘法器和N位被乘数乘积的二进制乘法器电路包括产生具有M行和M + N列的原始加法器位矩阵和矩阵减法电路的乘法器电路。 在矩阵简化电路中，对于具有三个或更多个原始加法器位的矩阵的每一列，三个位组被输入到全加法器电路中，该加法器电路输出该列的和位和该列的进位位在下一个最高有效位 位位置。 对于具有三个或更少的原始加和位的列，并且具有尚未减少到两个或更少位的最低有效列位置，两位组被输入到半加法器电路中，该半加法器电路输出该列的和位并携带 位在下一个最高有效位位置的列。 对于每列，通过对列中的每一组三位使用全加器电路，并通过使用半加法器电路对列中的两位的任何剩余组执行迭代减少。 减少继续，直到矩阵的每一列减少到两个或更少位。 剩余的两行位可以输入到两级进位传播加法器电路，以输出等于乘积的和。

公开(公告)号：US4805131A

公开(公告)日：1989-02-14

申请号：US72161

申请日：1987-07-09

申请人： Matthew J. Adiletta ,  Virginia C. Lamere

发明人： Matthew J. Adiletta ,  Virginia C. Lamere

IPC分类号： G06F7/494 ,  G06F7/50 ,  G06F7/506 ,  G06F7/508

CPC分类号： G06F7/494 ,  G06F2207/4921 ,  G06F2207/4924

摘要： The binary coded decimal (BCD) adder circuit for adding two BCD encoded operands and for producing a BCD encoded sum includes a bank of parallel full adder circuits as a first stage which generate an intermediate sum vector and an intermediate carry vector from the sum of the operands and a precorrection factor. A second stage of the BCD adder circuit includes carry lookahead adder circuitry receiving as inputs the intermediate sum vector and the intermediate carry vector and producing a propagate vector and a final carry vector. The third stage of the BCD adder circuit conditionally modifies the propagate vector to form the BCD encoded sum according to bits of the intermediate carry vector and the final carry vector as inputs.