公开(公告)号：US20190235877A1

公开(公告)日：2019-08-01

申请号：US16383212

申请日：2019-04-12

申请人： Intel Corporation

发明人： Mohammad ABDALLAH

IPC分类号： G06F9/38 ,  H04L12/28 ,  G06F12/00 ,  G06F9/46 ,  G06F15/173 ,  G06F9/30 ,  G06F13/00 ,  H04L12/933 ,  G06F12/0886 ,  G06F12/0853

CPC分类号： G06F9/3885 ,  G06F9/3004 ,  G06F9/3853 ,  G06F9/462 ,  G06F12/00 ,  G06F12/0853 ,  G06F12/0886 ,  G06F13/00 ,  G06F15/17318 ,  G06F2212/1041 ,  G06F2212/1056 ,  H04L12/28 ,  H04L49/1523

摘要： A method and apparatus including a cache controller coupled to a cache memory, wherein the cache controller receives a plurality of cache access requests, performs a pre-sorting of the plurality of cache access requests by a first stage of the cache controller to order the plurality of cache access requests, wherein the first stage functions by performing a presorting and pre-clustering process on the plurality of cache access requests in parallel to map the plurality of cache access requests from a first position to a second position corresponding to ports or banks of a cache memory, performs the combining and splitting of the plurality of cache access request by a second stage of the cache controller, and applies the plurality of cache access requests to the cache memory at line speed.

公开(公告)号：US20180095929A1

公开(公告)日：2018-04-05

申请号：US15281376

申请日：2016-09-30

申请人： INTEL CORPORATION

发明人： Zoran Zivkovic ,  Aleksandar Beric

IPC分类号： G06F15/173 ,  G11C7/22 ,  G11C7/10 ,  G06F3/06 ,  G06F13/42

CPC分类号： G06F15/17318 ,  G06F13/4234 ,  G06F13/4286 ,  G06F15/8061 ,  G11C8/12

摘要： An apparatus for localized and random data access is described herein. The apparatus includes a multi-bank memory, a queue, and an output buffer. The multi-bank memory is to store addresses locations of imaging data. The queue corresponds to each bank of the multi-bank memory, and the queue is to store addresses from the multi-bank memory for data access. The output buffer is to store data accessed based on addresses from the queue.

公开(公告)号：US09864759B2

公开(公告)日：2018-01-09

申请号：US13170490

申请日：2011-06-28

申请人： Ballav Bihani ,  Patrik Torstensson ,  Adam Messinger ,  Naresh Revanuru

发明人： Ballav Bihani ,  Patrik Torstensson ,  Adam Messinger ,  Naresh Revanuru

IPC分类号： G06F12/00 ,  G06F17/30 ,  H04L29/06 ,  G06F15/173 ,  H04L12/24 ,  H04L12/931 ,  H04L29/08 ,  G06F9/455

CPC分类号： G06F17/30286 ,  G06F9/45504 ,  G06F15/17318 ,  G06F17/30368 ,  G06F17/30584 ,  H04L29/06088 ,  H04L41/042 ,  H04L41/0686 ,  H04L49/358 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1004 ,  H04L67/1027 ,  H04L67/1034 ,  H04L67/1095 ,  H04L67/14 ,  H04L67/142 ,  H04L67/146

摘要： Systems and methods are provided for providing scatter/gather data processing. In accordance with an embodiment, a such a system can include a cluster of one or more high performance computing systems, each including one or more processors and a high performance memory. The cluster communicates over an InfiniBand network. The system can also include a middleware environment, executing on the cluster, that includes one or more application server instances. The system can further include a plurality of muxers. Each application server instance includes at least one muxer, and each muxer is operable to collect data from a plurality of locations in the high performance memory, and transfer the data in bulk.

公开(公告)号：US09830285B2

公开(公告)日：2017-11-28

申请号：US14882867

申请日：2015-10-14

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09824038B2

公开(公告)日：2017-11-21

申请号：US14882897

申请日：2015-10-14

申请人： Intel Corporation

发明人： Gilbert Wolrich ,  Debra Bernstein ,  Daniel Cutter ,  Christopher Dolan ,  Matthew J. Adiletta

IPC分类号： G06F13/20 ,  G06F12/0806 ,  G06F12/06 ,  G06F12/02 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G06F15/76 ,  G06F15/173 ,  G11C7/10 ,  G06F12/10 ,  G06F12/109

CPC分类号： G06F13/20 ,  G06F3/0622 ,  G06F3/0661 ,  G06F3/0679 ,  G06F12/0223 ,  G06F12/0284 ,  G06F12/06 ,  G06F12/0806 ,  G06F12/10 ,  G06F12/109 ,  G06F13/28 ,  G06F13/4027 ,  G06F15/17318 ,  G06F15/76 ,  G06F2212/1041 ,  G06F2212/206 ,  G06F2212/251 ,  G11C7/1033 ,  G11C7/1072

摘要： The disclosure includes, in general, among other aspects, an apparatus having multiple programmable units integrated within a processor. The apparatus has circuitry to map addresses in a single address space to resources within the multiple programmable units where the single address space includes addresses for different ones of the resources in different ones of the multiple programmable units and where there is a one-to-one correspondence between respective addresses in the single address space and resources within the multiple programmable units.

公开(公告)号：US09811541B2

公开(公告)日：2017-11-07

申请号：US13167636

申请日：2011-06-23

申请人： Naresh Revanuru ,  Lenny Phan ,  Scott Oaks

发明人： Naresh Revanuru ,  Lenny Phan ,  Scott Oaks

IPC分类号： G06F17/30 ,  H04L29/06 ,  G06F15/173 ,  H04L12/24 ,  H04L12/931 ,  H04L29/08 ,  G06F9/455

CPC分类号： G06F17/30286 ,  G06F9/45504 ,  G06F15/17318 ,  G06F17/30368 ,  G06F17/30584 ,  H04L29/06088 ,  H04L41/042 ,  H04L41/0686 ,  H04L49/358 ,  H04L67/02 ,  H04L67/10 ,  H04L67/1002 ,  H04L67/1004 ,  H04L67/1027 ,  H04L67/1034 ,  H04L67/1095 ,  H04L67/14 ,  H04L67/142 ,  H04L67/146

摘要： A system and method can support in-memory session replication in a server cluster using a lazy deserialization approach. The server cluster can include a primary application server and a secondary application server. The primary application server operates to receive a request associated with a session from a client and maintains session information associated with the session. Based on the session information, the primary application server can responds to the client. The secondary application server operates to receive and maintain serialized session information from the primary application server. The secondary application server operates to update the serialized session information based on one or more session updates received from the primary application server. When the primary application server fails, the secondary application server can generate deserialized session information based on the updated serialized session information and responds to the client.

公开(公告)号：US09740499B2

公开(公告)日：2017-08-22

申请号：US14213909

申请日：2014-03-14

申请人： Intel Corporation

发明人： Mohammad Abdallah

IPC分类号： H04W4/00 ,  G06F9/38 ,  H04L12/933 ,  G06F9/30 ,  G06F13/00 ,  G06F15/173 ,  G06F9/46 ,  G06F12/00 ,  H04L12/28

CPC分类号： G06F9/3885 ,  G06F9/3004 ,  G06F9/3853 ,  G06F9/462 ,  G06F12/00 ,  G06F12/0853 ,  G06F12/0886 ,  G06F13/00 ,  G06F15/17318 ,  G06F2212/1041 ,  G06F2212/1056 ,  H04L12/28 ,  H04L49/1523

摘要： A method for line speed interconnect processing. The method includes receiving initial inputs from an input communications path, performing a pre-sorting of the initial inputs by using a first stage interconnect parallel processor to create intermediate inputs, and performing the final combining and splitting of the intermediate inputs by using a second stage interconnect parallel processor to create resulting outputs. The method further includes transmitting the resulting outputs out of the second stage at line speed.

公开(公告)号：US09684629B2

公开(公告)日：2017-06-20

申请号：US15138210

申请日：2016-04-25

申请人： International Business Machines Corporation

发明人： Timothy O. Dickson ,  Daniel M. Dreps ,  Frank D. Ferraiolo ,  Douglas J. Joseph

IPC分类号： G06F9/00 ,  G06F13/00 ,  G06F15/173 ,  G06F13/42 ,  G06F11/30 ,  G06F13/16 ,  G06F13/24 ,  G06F15/80 ,  G06F19/00 ,  H04B1/38 ,  H04L12/54

CPC分类号： G06F15/17318 ,  G06F9/00 ,  G06F11/3058 ,  G06F13/00 ,  G06F13/1673 ,  G06F13/24 ,  G06F13/4217 ,  G06F13/4282 ,  G06F15/803 ,  G06F19/00 ,  H04B1/38 ,  H04L12/56 ,  Y02D10/14 ,  Y02D10/151

摘要： A calibratable communications link includes multiple parallel lines. Calibration is performed at dynamically variable and/or interruptible intervals determined by an automated mechanism. Calibration is preferably initiated responsive to a command generated by an executable software process, which initiates calibration responsive to detection of a probable impending need as indicated by, e.g., temperature change, calibrated parameter drift, error rate, etc. Calibration is also preferably initiated according to probable minimal disruption of device function, as indicated by low activity level. Furthermore, in one aspect calibration may be temporarily suspended to transmit data and then resumed.

公开(公告)号：US09411777B2

公开(公告)日：2016-08-09

申请号：US14487251

申请日：2014-09-16

申请人： International Business Machines Corporation

发明人： Charles J. Archer ,  Nysal Jan K. A. ,  Sameh S. Sharkawi

IPC分类号： G06F9/54 ,  G06F15/173

CPC分类号： G06F15/17318 ,  G06F9/5066 ,  G06F9/542

摘要： In a parallel computer, performing a rooted-v collective operation by an operational group of compute nodes includes: identifying, in source code by a collective algorithm selection optimizing module, a gather operation followed by a rooted-v collective operation; replacing, by the collective algorithm selection optimizing module, the gather operation with an allgather operation; executing, by the compute nodes, the allgather operation; selecting, by each compute node in dependence upon results of the allgather operation, an algorithm for effecting the rooted-v collective operation; and executing, by each compute node, the rooted-v collective operation with the selected algorithm.

摘要翻译： 在并行计算机中，由计算节点的操作组执行root-v集合操作包括：在源代码中通过集体算法选择优化模块识别收集操作，随后是根v集合操作; 通过集合算法选择优化模块替换采集操作; 由计算节点执行allgather操作; 根据整个算法的结果，由每个计算节点选择用于实现根v集合操作的算法; 并且通过所选择的算法由每个计算节点执行带root-v的集合操作。

公开(公告)号：US09390054B2

公开(公告)日：2016-07-12

申请号：US14053171

申请日：2013-10-14

申请人： International Business Machines Corporation

发明人： Kristan D. Davis ,  Daniel A. Faraj

IPC分类号： G06F15/173

CPC分类号： G06F15/17318

摘要： In a parallel computer, a largest logical plane from a plurality of logical planes formed of compute nodes of a subcommunicator may be identified by: identifying, by each compute node of the subcommunicator, all logical planes that include the compute node; calculating, by each compute node for each identified logical plane that includes the compute node, an area of the identified logical plane; initiating, by a root node of the subcommunicator, a gather operation; receiving, by the root node from each compute node of the subcommunicator, each node's calculated areas as contribution data to the gather operation; and identifying, by the root node in dependence upon the received calculated areas, a logical plane of the subcommunicator having the greatest area.

摘要翻译： 在并行计算机中，可以通过以下方式来识别来自由子通信器的计算节点形成的多个逻辑平面的最大逻辑平面：由子通信器的每个计算节点识别包括计算节点的所有逻辑平面; 由每个计算节点针对包括计算节点的每个识别的逻辑平面计算所识别的逻辑平面的面积; 通过子通信器的根节点发起收集操作; 由根节点从子通信器的每个计算节点接收每个节点的计算区域作为收集操作的贡献数据; 并且根据所接收的计算区域，根节点识别具有最大面积的子通信器的逻辑平面。