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102 条记录 (耗时 0.031 秒)

    Read lock miss control and queue management
    4.
    发明授权
    Read lock miss control and queue management 有权
    读锁定错误控制和队列管理

    公开(公告)号：US06681300B2

    公开(公告)日：2004-01-20

    申请号：US09969436

    申请日：2001-10-02

    申请人： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    发明人： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    IPC分类号： G06F1200

    CPC分类号： G06F9/52

    摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if the read lock memory reference request is requesting access to an unlocked memory location and the read lock miss queue contains at least one read lock memory reference request.

    摘要翻译： 管理对随机存取存储器的存储器访问包括获取读取锁定存储器引用请求并将读取的锁定存储器引用请求放置在读取锁定未命中队列的结尾，如果读取锁定存储器引用请求访问未锁定的存储器位置并读取 锁定未命中队列至少包含一个读锁定存储器引用请求。

    Read lock miss control and queue management
    5.
    发明授权
    Read lock miss control and queue management 有权
    读锁定错误控制和队列管理

    公开(公告)号：US06324624B1

    公开(公告)日：2001-11-27

    申请号：US09473798

    申请日：1999-12-28

    申请人： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    发明人： Gilbert Wolrich ,  Daniel Cutter ,  William Wheeler ,  Matthew J. Adiletta ,  Debra Bernstein

    IPC分类号： G06F1318

    CPC分类号： G06F9/52

    摘要： Managing memory access to random access memory includes fetching a read lock memory reference request and placing the read lock memory reference request at the end of a read lock miss queue if (1) the read lock memory reference request is requesting access to an unlocked memory location and (2) the read lock miss queue contains at least one read lock memory reference request.

    摘要翻译： 管理对随机存取存储器的存储器访问包括获取读锁定存储器引用请求并将读锁定存储器引用请求放置在读锁定未命中队列的末尾，如果（1）读锁定存储器引用请求正在请求访问解锁的存储器位置 和（2）读取锁定未命中队列至少包含一个读取锁定存储器引用请求。

    Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms
    9.
    发明授权
    Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms 有权
    多处理器基础设施，通过单独的数据总线，控制总线和支持机制的多个实例提供灵活的带宽分配

    公开(公告)号：US07225281B2

    公开(公告)日：2007-05-29

    申请号：US10212944

    申请日：2002-08-05

    申请人： Mark B. Rosenbluth ,  Gilbert Wolrich ,  Debra Bernstein ,  Myles J. Wilde ,  Matthew J. Adiletta

    发明人： Mark B. Rosenbluth ,  Gilbert Wolrich ,  Debra Bernstein ,  Myles J. Wilde ,  Matthew J. Adiletta

    IPC分类号： G06F13/00

    CPC分类号： G06F13/364 ,  G06F13/4004

    摘要： A bus mechanism to control information exchanges between bus masters and bus targets over a bus structure that includes separate command, push and pull data buses. Commands are generated by bus masters and are interpreted by bus targets on a per-target basis. Each bus target controls the servicing of a command intended for such target by controlling the transfer of push data over the push bus to a bus master specified in the command as a destination, for a push operation type, and by controlling the transfer of pull data over the pull bus to the target from a bus master specified in the command as a destination, for a pull operation type. Arbitration logic associated with each bus is used to control the flow of the information exchanges on that bus.

    摘要翻译： 一种总线机制，用于通过总线结构控制总线主机和总线目标之间的信息交换，该总线结构包括单独的命令，推拉数据总线。 命令由公交车主人生成，并由每个目标的公交车目标解释。 每个总线目标通过控制通过推送总线将推送数据传送到作为目的地的命令中指定的总线主机，用于推送操作类型，并通过控制拉动数据的传送来控制对该目标的命令的服务 通过从作为目的地的命令中指定的总线主机到目的地的拉取总线，用于拉动操作类型。 与每个总线相关联的仲裁逻辑用于控制该总线上的信息交换流。

    Context pipelines
    10.
    发明授权
    Context pipelines 有权
    上下文管道

    公开(公告)号：US07181594B2

    公开(公告)日：2007-02-20

    申请号：US10057723

    申请日：2002-01-25

    申请人： Hugh M. Wilkinson, III ,  Mark B. Rosenbluth ,  Matthew J. Adiletta ,  Debra Bernstein ,  Gilbert Wolrich

    发明人： Hugh M. Wilkinson, III ,  Mark B. Rosenbluth ,  Matthew J. Adiletta ,  Debra Bernstein ,  Gilbert Wolrich

    IPC分类号： G06F9/312

    CPC分类号： G06F9/462 ,  G06F9/30123

    摘要： A method of parallel hardware-based multithreaded processing is described. The method includes assigning tasks for packet processing to programming engines and establishing pipelines between programming stages, which correspond to the programming engines. The method also includes establishing contexts for the assigned tasks on the programming engines and using a software controlled cache such as a CAM to transfer data between next neighbor registers residing in the programming engines.

    摘要翻译： 描述了一种基于并行硬件的多线程处理方法。 该方法包括将分组处理的任务分配给编程引擎，并在与编程引擎相对应的编程阶段之间建立管线。 该方法还包括为编程引擎上分配的任务建立上下文，并使用诸如CAM的软件控制的高速缓存来在驻留在编程引擎中的下一个相邻寄存器之间传送数据。