公开(公告)号：US07445088B2

公开(公告)日：2008-11-04

申请号：US10780587

申请日：2004-02-19

Applicant: Takashi Watanabe ,  Osamu Takahashi

Inventor： Takashi Watanabe ,  Osamu Takahashi

IPC: F01M1/00 ,  F01M9/06 ,  F16N7/26 ,  F16N7/28

CPC classification number: F16H57/0483 ,  F16H57/0427

Abstract: A differential for a wheeled motor vehicle comprises a differential gear unit, and a differential case for housing therein the differential gear unit. The differential case is rotatable about its rotation axis in normal and reverse directions at a position above an oil level of a lubricating oil. The differential case includes a portion having an oil inlet opening formed therethrough, the oil inlet opening communicating the interior of the differential case with the outside of the same; and an oil dipping up structure that dips up the lubricating oil to force the same to enter the interior of the differential case through the oil inlet opening when the differential case rotates about the rotation axis.

Abstract translation: 用于轮式机动车辆的差速器包括差速齿轮单元和用于在其中容纳差速齿轮单元的差速器壳体。 差速器壳体可在其在润滑油的油位上方的位置沿其正向和反向方向围绕其旋转轴线旋转。 差速器壳体包括具有贯穿其中形成的进油口的部分，所述进油口将差速器壳体的内部与其外部连通; 以及当差速器壳体围绕旋转轴线旋转时，油浸液体结构使润滑油下降，以迫使其同时通过进油口进入差速器壳体的内部。

公开(公告)号：US07444525B2

公开(公告)日：2008-10-28

申请号：US11137234

申请日：2005-05-25

Applicant: Hiroshi Yoshihara ,  Sang Hoo Dhong ,  Osamu Takahashi ,  Takaaki Nakazato

Inventor： Hiroshi Yoshihara ,  Sang Hoo Dhong ,  Osamu Takahashi ,  Takaaki Nakazato

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32

CPC classification number: H03K19/0016

Abstract: Methods and apparatus provide for enabling a digital circuit by biasing at least one switch transistor ON such that a voltage potential of a virtual ground node is substantially equal to a voltage potential of a ground node for a power supply to the digital circuit, wherein the digital circuit is implemented using a plurality of transistors in a silicon-on-insulator (SOI) arrangement and at least some of the transistors are referenced to the virtual ground node; and disabling the digital circuit by biasing a gate terminal of the switch transistor below the voltage potential of the ground node.

Abstract translation: 方法和装置提供了通过使至少一个开关晶体管导通来使能数字电路，使得虚拟接地节点的电压电位基本上等于用于数字电路的电源的接地节点的电压电位，其中数字 电路使用绝缘体上硅（SOI）布置中的多个晶体管实现，并且至少一些晶体管参考虚拟接地节点; 以及通过将所述开关晶体管的栅极端子偏压到所述接地节点的电压电位以下来禁止所述数字电路。

公开(公告)号：US07394579B2

公开(公告)日：2008-07-01

申请号：US10618626

申请日：2003-07-15

Applicant: Osamu Takahashi

Inventor： Osamu Takahashi

IPC: H04N1/04

CPC classification number: H04N1/0411 ,  H04N1/0402 ,  H04N1/0449 ,  H04N1/0458 ,  H04N1/193 ,  H04N1/40068

Abstract: An image reading apparatus of the present invention converts respective pixel signals outputted from first, second and third shift registers to pixel data in an analog frontend IC and outputs pixel data as a serial data stream in a predetermined pattern. The address setting unit repeats add and subtract operation to the initial value according to the output pattern of the pixel data from the analog frontend IC to calculate pixel positions of the respective pixel data, and sets memory addresses corresponding to the pixel positions as destination memory addresses of the pixel data in an address register RR. The memory writing control unit writes the pixel data obtained from the analog frontend IC via a data sampling control unit in areas in the memory which correspond to the destination memory addresses. As a result, the amount of memory necessary for storing the pixel data can be reduced, and sorting operation of the pixel data can be executed with fewer memory access times.

Abstract translation: 本发明的图像读取装置将从第一移位寄存器，第二移位寄存器和第三移位寄存器输出的各像素信号转换为模拟前端IC中的像素数据，并将像素数据作为串行数据流以预定模式输出。 地址设定单元根据来自模拟前端IC的像素数据的输出图案，对初始值进行加减运算，计算出各像素数据的像素位置，并将与像素位置对应的存储器地址设定为目的地存储器地址 的地址寄存器RR中的像素数据。 存储器写入控制单元经由数据采样控制单元将从模拟前端IC获得的像素数据写入存储器中对应于目的地存储器地址的区域中。 结果，可以减少存储像素数据所需的存储量，并且可以以更少的存储器访问时间执行像素数据的排序操作。

公开(公告)号：US20070202446A1

公开(公告)日：2007-08-30

申请号：US11445325

申请日：2006-06-02

Applicant: Osamu Takahashi ,  Tetsuo Yaegashi

Inventor： Osamu Takahashi ,  Tetsuo Yaegashi

IPC: G03F7/26

CPC classification number: G03F7/42 ,  H01L21/31127 ,  H01L21/67063 ,  H01L21/6708

Abstract: In the step of removing the photo-resist film formed on a substrate, dry ice particles, with a predetermined particle size, are blasted onto the photo-resist film at a predetermined pressure in a state of heating the substrate at room temperature or higher, such as 30 to 200° C., preferably at about 100° C.

Abstract translation: 在去除形成在基板上的光刻胶膜的步骤中，在室温或更高温度的基板加热的状态下，以预定压力将具有预定粒径的干冰颗粒喷射到光致抗蚀剂膜上， 例如30至200℃，优选约100℃

公开(公告)号：US07218152B2

公开(公告)日：2007-05-15

申请号：US11033612

申请日：2005-01-12

Applicant: Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

Inventor： Hiroaki Murakami ,  Osamu Takahashi ,  Shoji Onishi

IPC: H03K19/20

CPC classification number: H03K19/1737

Abstract: Systems and methods for reducing the power consumption associated with the capacitance of sections of a multiplexer are disclosed. At each cycle, a timing signal is selectively sent only to sections of the multiplexer that include active logic. A plurality of control signals is received for processing by a corresponding plurality of input selection circuits. A plurality of additional inputs corresponding to the plurality of input selection circuits may also be received. In one embodiment, each input selection circuit is configured to output a corresponding input signal if a corresponding control signal is asserted and a timing signal is made available to the input selection circuit. To avoid unnecessary power consumption associated with the capacitance of various portions of the multiplexer, the timing signal is only asserted to a portion of the multiplexer at any given clock cycle according to the values of the control signals.

Abstract translation: 公开了用于降低与多路复用器的部分的电容相关联的功耗的系统和方法。 在每个周期，定时信号仅选择性地仅发送到包括有效逻辑的多路复用器的部分。 多个控制信号被接收用于由相应的多个输入选择电路进行处理。 还可以接收对应于多个输入选择电路的多个附加输入。 在一个实施例中，每个输入选择电路被配置为如果相应的控制信号被断言并且使定时信号对输入选择电路可用，则输出相应的输入信号。 为了避免与多路复用器的各个部分的电容相关联的不必要的功率消耗，定时信号仅根据控制信号的值以任何给定的时钟周期被认定到多路复用器的一部分。

公开(公告)号：US20070079193A1

公开(公告)日：2007-04-05

申请号：US11550997

申请日：2006-10-19

Applicant: Sang Dhong ,  Joel Silberman ,  Osamu Takahashi

Inventor： Sang Dhong ,  Joel Silberman ,  Osamu Takahashi

IPC: G01R31/28

CPC classification number: H03K3/356113 ,  G01R31/318541

Abstract: A scannable latch is disclosed. The scannable latch includes a dynamic circuit, two cross-coupled NAND gates coupled to the dynamic circuit, and a pair of stacked transistors coupled to the dynamic circuit. One of the stacked transistors is for receiving data signals, and the other stacked transistors is for receiving scan in signals.

Abstract translation: 公开了可扫描的闩锁。 可扫描锁存器包括动态电路，耦合到动态电路的两个交叉耦合NAND门和耦合到动态电路的一对堆叠晶体管。 堆叠晶体管中的一个用于接收数据信号，而另一个堆叠晶体管用于接收扫描信号。

公开(公告)号：US20070077373A1

公开(公告)日：2007-04-05

申请号：US11528260

申请日：2006-09-28

Applicant: Hiromoto Haruta ,  Osamu Takahashi ,  Mamoru Sakurazawa

Inventor： Hiromoto Haruta ,  Osamu Takahashi ,  Mamoru Sakurazawa

IPC: C09K19/00

CPC classification number: C09K19/2007 ,  C09K19/22 ,  C09K19/28 ,  C09K19/3068 ,  C09K19/3411 ,  C09K19/3477 ,  C09K19/3497 ,  C09K2019/0429 ,  C09K2019/328 ,  C09K2219/03 ,  G02B5/3016 ,  G02B5/3033 ,  G02B5/3083 ,  Y10T428/1041

Abstract: A polymer film, which comprises: at least one liquid crystalline compound; and a compound having a dielectric constant ε of 4.0 or more, wherein a haze of the polymer film is 1.5% or less; and a polarizing plate and a liquid crystal display device using the polymer film.

Abstract translation: 一种聚合物膜，其包含：至少一种液晶化合物; 和介电常数ε为4.0以上的化合物，其中，所述聚合物膜的雾度为1.5％以下; 以及使用该聚合物膜的偏光板和液晶显示装置。

公开(公告)号：US20070057591A1

公开(公告)日：2007-03-15

申请号：US10573851

申请日：2004-09-27

Applicant: Osamu Takahashi ,  Tomoyuki Mizuguchi ,  Shinichi Oi

Inventor： Osamu Takahashi ,  Tomoyuki Mizuguchi ,  Shinichi Oi

IPC: H02K11/00 ,  H02K1/00

CPC classification number: H02K3/28 ,  H02K3/522 ,  H02K15/095 ,  H02K29/03

Abstract: In order to achieve a higher level of efficiency and greater output without complicating the manufacturing process or increasing production costs, an electromagnetic motor according to the present invention adopts a Δ connection structure, which includes a u-phase coil winding unit, a v-phase coil winding unit and a w-phase coil winding unit radially extending from a stator fixed to a rotating shaft and set with a phase difference relative to one another and a first feeding terminal, a second feeding terminal and a third feeding terminal through which a predetermined current is supplied to coils at the individual phases. The electromagnetic motor is characterized in that coils are wound at least twice over through a sequence; the first feeding terminal→the u-phase coil winding unit→the second feeding terminal→the v-phase coil winding unit→the third feeding terminal→the w-phase, winding unit, so as to form at least two coil layers at each coil winding unit among the u-phase coil winding unit, the v-phase coil winding unit and the w-phase coil winding unit.

Abstract translation: 为了实现更高的效率和更大的输出，而不会使制造过程复杂化或增加生产成本，根据本发明的电磁马达采用三角形连接结构，其包括U相线圈绕组单元，v相 线圈绕组单元和w相线圈绕组单元，其从固定在旋转轴上的定子径向延伸并且相对于彼此设定为相位差;以及第一馈电端子，第二馈电端子和第三馈电端子，预定 电流在各个相位被提供给线圈。 电磁马达的特征在于线圈通过一个顺序缠绕至少两次; 第一馈电端子 - > U相绕组单元 - >第二馈电端子 - > v相绕组单元 - >第三馈电端子 - > w相绕组单元，以形成至少 U相线圈卷绕单元，v相线圈卷绕单元和w相线圈卷绕单元中的每个线圈卷绕单元处的两个线圈层。

公开(公告)号：US07170316B2

公开(公告)日：2007-01-30

申请号：US10982018

申请日：2004-11-05

Applicant: Sang Hoo Dhong ,  Brian K. Flachs ,  Joel A. Silberman ,  Osamu Takahashi

Inventor： Sang Hoo Dhong ,  Brian K. Flachs ,  Joel A. Silberman ,  Osamu Takahashi

IPC: H03K19/177 ,  G06F7/38

CPC classification number: H03K19/1772

Abstract: A programmable logic array (PLA) latch is disclosed. The PLA latch includes a first logic array, a second logic array and only one output latch. The second logic array is coupled to the first logic array. The output latch is coupled to the second logic array.

Abstract translation: 公开了一种可编程逻辑阵列（PLA）锁存器。 PLA锁存器包括第一逻辑阵列，第二逻辑阵列和仅一个输出锁存器。 第二逻辑阵列耦合到第一逻辑阵列。 输出锁存器耦合到第二逻辑阵列。

公开(公告)号：US07167417B2

公开(公告)日：2007-01-23

申请号：US10752089

申请日：2004-01-07

Applicant: Hidehiro Akahane ,  Osamu Takahashi

Inventor： Hidehiro Akahane ,  Osamu Takahashi

IPC: G04C11/00 ,  G06F1/04 ,  G04B19/04

CPC classification number: G04R20/00 ,  G04R20/28 ,  G04R60/14

Abstract: A time correction system has a timepiece with pointers for displaying the time, and a correction instruction device. The correction instruction device has a timing section for timing reference time data, a time input section for inputting pointed time data corresponding to the time indicated by the pointers, a comparison section for comparing the reference time data and the pointed time data, and a communication section for outputting a correction instruction signal based on the results of this comparison to the pointer type timepiece. The pointer type timepiece has an external signal detection circuit for receiving the correction instruction signal, a drive control section for controlling the driving of the pointers, and a time correction control circuit for matching the readings of the pointers with the reference time data based on the received correction instruction signal.

Abstract translation: 时间校正系统具有用于显示时间的指针的钟表和校正指示装置。 校正指示装置具有用于定时基准时间数据的定时部分，用于输入与指针所指示的时间相对应的指向时间数据的时间输入部分，用于比较参考时间数据和指示时间数据的比较部分，以及通信 部分，用于基于与指针型时计的该比较的结果输出校正指令信号。 指针式时计具有用于接收校正指示信号的外部信号检测电路，用于控制指针的驱动的驱动控制部，以及基于时钟校正控制电路，用于将指针的读数与基准时间数据进行匹配 接收到校正指令信号。