公开(公告)号：US10964243B2

公开(公告)日：2021-03-30

申请号：US16515880

申请日：2019-07-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Lijun Yuan ,  Xing Yao ,  Guangliang Shang ,  Haoliang Zheng ,  Zhenyu Zhang

IPC: G11C19/00 ,  G09G3/20 ,  G09G3/36 ,  G11C19/28

Abstract: A shift register circuit according to an embodiment of the present disclosure includes an input sub-circuit and N-stage output sub-circuits. The input sub-circuit is configured to transmit an input signal to a pull up node at a first stage. The output sub-circuit at each stage is configured to transmit a clock signal from a clock signal terminal at a same stage to an output signal terminal at the same stage under the control of a pull-up node at the same stage. The output sub-circuit at each stage is further configured to transmit a signal transmitted to an output signal terminal at the same stage to a pull-up node at an immediately subsequent stage under the control of a shift control signal from a shift control signal terminal at the same stage.

公开(公告)号：US20190139475A1

公开(公告)日：2019-05-09

申请号：US16126032

申请日：2018-09-10

Applicant: BOE Technology Group Co., Ltd.

Inventor： Zhichong Wang ,  Haoliang Zheng ,  Seungwoo Han ,  Guangliang Shang ,  Mingfu Han ,  Lijun Yuan ,  Xing Yao

IPC: G09G3/20 ,  G11C19/28

Abstract: A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit.

公开(公告)号：US10255985B2

公开(公告)日：2019-04-09

申请号：US15503830

申请日：2016-08-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Mingfu Han ,  Guangliang Shang ,  Yuanbo Zhang ,  Yujie Gao ,  Yan Yan ,  Yingmeng Miao ,  Seungwoo Han ,  Zhihe Jin ,  Xing Yao ,  Haoliang Zheng

IPC: G11C19/28 ,  G09G3/20

Abstract: A supplement resetting module for a gate driver circuit, including a pull-up control unit, a pull-down control unit, a clock signal input end, a predetermined level input end, a first control signal input end, a second control signal input end and a signal output end. A control end of the pull-up control unit is connected to the clock signal input end, an output end of the pull-up control unit is connected to the signal output end, a first control end of the pull-down control unit is connected to the first control signal input end, a second control end of the pull-down control unit is connected to the second control signal input end, an input end of the pull-down control unit is connected to the predetermined level input end, and an output end of the pull-down control unit is connected to the signal output end.

公开(公告)号：US10210835B2

公开(公告)日：2019-02-19

申请号：US15656419

申请日：2017-07-21

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Mingfu Han ,  Guangliang Shang ,  Seungwoo Han ,  Zhihe Jin ,  Xing Yao ,  Haoliang Zheng ,  Lijun Yuan ,  Zhichong Wang

IPC: G09G3/36 ,  G09G3/30

Abstract: The present invention discloses a gate driver on array circuit and a driving method thereof, and a display device. The gate driver on array circuit comprises a first gate driver on array sub-circuit and a second gate driver on array sub-circuit; the first gate driver on array sub-circuit is configured to drive in a first working state which is a state in which no defect occurs in the first gate driver on array sub-circuit; the second gate driver on array sub-circuit is configured to drive in a second working state which is a state in which a defect occurs in the first gate driver on array sub-circuit. The present invention improves the yield rate of the gate driver on array circuit.

公开(公告)号：US10186221B2

公开(公告)日：2019-01-22

申请号：US15512284

申请日：2016-02-19

Applicant: Boe Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Haoliang Zheng

IPC: G11C19/00 ,  G09G3/36 ,  G11C19/28 ,  G11C8/04 ,  G11C19/18

Abstract: A shift register, a driving method, a gate driving circuit and a display device are disclosed. The input module controls the potential of the first node. The first reset module controls the potential of the first node. The second reset module controls the potential of the driving signal output terminal. The first output module controls the potential of the driving signal output terminal under the control of the first node. The second output module controls the potential of the driving signal output terminal under the control of the second node. The pull-down driving module controls the potentials of the first node and the second node. Since the node control signal at the node control signal terminal can eliminate the noise on the first node resulting from the change in the first clock signal, the output stability of the shift register can be improved.

公开(公告)号：US20180286303A1

公开(公告)日：2018-10-04

申请号：US15793957

申请日：2017-10-25

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Jung Chul Gyu ,  Seung Woo Han ,  Haoliang Zheng ,  Mingfu Han ,  Zhihe Jin ,  Im- Yun- Sik ,  Jing Lv ,  Xue Dong

IPC: G09G3/20 ,  H03K17/687 ,  G09G5/00

Abstract: The present disclosure relates to a pixel driving circuit, a driving method thereof, and a display apparatus, to realize switch between resolutions of the display apparatus which is driven by the pixel driving circuit. The pixel driving circuit comprises: r first data lines and k second data lines, each of the first data lines has a first switch unit provided thereon, and is connected to q second data lines through a second switch unit, and the first switch unit and the second switch unit are connected to a signal control unit respectively; and the signal control unit is configured to control the first switch unit to be turned on and the second switch unit to be turned off when display is to be performed at a first resolution, and control the first switch unit to be turned off and the second switch unit to be turned on when display is to be performed at a second resolution, wherein the first resolution is greater than the second resolution.