-
公开(公告)号：US12113060B2
公开(公告)日：2024-10-08
申请号：US17424900
申请日：2020-10-28
Inventor： Tingting Wang , Yan Yan , Qi Wang , Li Tian
IPC: H01L27/02 , G02F1/1368 , H01L27/12 , H01R13/703 , H05K1/02 , G09G3/36
CPC classification number: H01L27/0296 , G02F1/1368 , H01L27/124 , H01L27/1244 , H01L27/1255 , H01R13/7031 , H05K1/0259 , G09G3/36 , H01L27/0288
Abstract: Provided is a display substrate including a substrate, wherein the substrate includes a display region and a peripheral region located at the periphery of the display region. A GOA circuit, a first common electrode lead, a first capacitor and at least one first ESD unit are provided in the peripheral region. The GOA circuit includes a plurality of GOA units and STV signal lines electrically connected to at least one GOA unit. The first common electrode lead is connected to the STV signal line through at least one first ESD unit. A first capacitor electrode of the first capacitor is connected to the STV signal line, and a second capacitor electrode of the first capacitor is connected to the first common electrode lead.
-
公开(公告)号：US20240210766A1
公开(公告)日：2024-06-27
申请号：US18547390
申请日：2022-11-29
Inventor： Tingting Wang , Xu Wang , Qi Wang , Yan Yan , Yu Ma , Xiaofeng Yin , Zhiqiang Ma , Tao Gong , Haoyan Ren
IPC: G02F1/1343 , G02F1/1362 , H01L27/12
CPC classification number: G02F1/134318 , G02F1/136209 , G02F1/136286 , H01L27/124
Abstract: An array substrate includes: a base substrate, a light shielding layer on a first surface of the base substrate, and a plurality of pixel units and a first common electrode bus on a second surface of the base substrate. The base substrate includes a display region, first and second peripheral regions. Orthographic projections of the pixel units on the base substrate are arranged in an array in the display region. At least part of an orthographic projection of the light shielding layer and at least part of an orthographic projection of the first common electrode bus on the base substrate are in the second peripheral region, and the first common electrode bus is electrically connected to the common electrode included in at least one pixel unit. A distribution density of the first common electrode bus in the first peripheral region is smaller than that in the second peripheral region.
-
3.发明授权公开(公告)号：US11910522B2
公开(公告)日：2024-02-20
申请号：US17523495
申请日：2021-11-10
Inventor： Tingting Wang , Qi Wang , Yan Yan
CPC classification number: H05K1/0213 , H05K1/028 , H05K1/09 , H05K2201/10128
Abstract: A flexible circuit board, a method for manufacturing the flexible circuit board, and a display device are provided. The flexible circuit board includes: a plurality of driving signal lines arranged with mutually insulate-gates, wherein the driving signal lines comprise at least two voltage signal lines arranged adjacent to each other; at least one isolation protecting line, the isolation protecting line being located between the two voltage signal lines arranged adjacent to each other.
-
公开(公告)号：US11893955B2
公开(公告)日：2024-02-06
申请号：US17435209
申请日：2021-02-07
Inventor： Tingting Wang , Qi Wang , Yan Yan , Xue Wang
IPC: G09G3/36
CPC classification number: G09G3/3696
Abstract: The present disclosure provides common voltage compensation method and device for display panel, a display panel, and a display device. The display panel includes a common electrode, a common voltage compensation unit, and common electrode lines. The common electrode lines are sequentially numbered according to a distance from the common voltage compensation unit, a number of the common electrode lines is n, and n is an integer greater than 8. The method includes: the common voltage compensation unit providing common voltage to the common electrode; the common voltage compensation unit detecting actual common voltage on one of N1-th common electrode line to N2-th common electrode line, N1 being a value rounded down from n/8, and N2 being a value rounded down from n/4; the common voltage compensation unit compensating the common voltage of the common electrode according to the detected actual common voltage.
-
公开(公告)号：US11830398B2
公开(公告)日：2023-11-28
申请号：US17434987
申请日：2020-12-28
Inventor： Yan Yan , Yu Ma , Weitao Chen , Xiaopeng Cui
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2300/0842 , G09G2310/0267 , G09G2310/0286
Abstract: A shift register circuit includes a first pull-down control sub-circuit and a first noise reduction sub-circuit. The first pull-down control sub-circuit includes a first transistor and a second transistor, and a ratio of a width-to-length ratio of a channel of the second transistor to a width-to-length ratio of a channel of the first transistor is greater than 5:1. The first pull-down control sub-circuit transmits, in response to a first voltage signal received at a first voltage signal terminal, the first voltage signal to a first pull-down node through the first transistor, and transmits a second voltage signal received at a second voltage signal terminal to the first pull-down node through the second transistor under control of a voltage of a pull-up node. The first noise reduction sub-circuit transmits the second voltage signal to the pull-up node under control of a voltage of the first pull-down node.
-
Patent Agency Ranking
公开(公告)号：US20190114951A1
公开(公告)日：2019-04-18
申请号：US15910117
申请日：2018-03-02
Abstract: The present disclosure provides a gate driving circuit and a display apparatus. The gate driving circuit comprises a plurality of cascaded shift registers, wherein the shift registers each comprise an input sub-circuit, an output sub-circuit, an output de-noising sub-circuit, a capacitor sub-circuit and a reset sub-circuit, wherein the output de-noising sub-circuit is electrically connected to a first reference voltage signal terminal, a second reference voltage signal terminal and an output signal terminal, and for each stage of shift register except for a first stage of shift register, the second reference voltage signal terminal is electrically connected to an input signal terminal of a stage of shift register immediately prior to the current stage of shift register.
-
7.发明授权Shift register unit, shift register, gate drive circuit and display apparatus 有权移位寄存器单元，移位寄存器，栅极驱动电路和显示装置公开(公告)号：US09257198B2
公开(公告)日：2016-02-09
申请号：US14548920
申请日：2014-11-20
Inventor： Yan Yan
IPC: H01L27/148 , G11C19/28 , G09G3/36
CPC classification number: G11C19/28 , G09G3/3611 , G09G3/3677 , G09G2310/0286
Abstract: To provide a shift register unit, which comprises a positive control signal input terminal, a reverse control signal input terminal, a first thin film transistor, a second thin film transistor, a positive input terminal, a reverse input terminal, a pull-up module and a first reset module, a gate of the first thin film transistor is connected with the positive input terminal, a first electrode of the first thin film transistor is connected with the positive control signal input terminal, a second electrode of the first thin film transistor is connected with a pull-up node of the pull-up module, a gate of the second thin film transistor is connected with the reverse input terminal, a first electrode of the second thin film transistor is connected with the pull-up node of the pull-up module, a second electrode of the second thin film transistor is connected with the reverse control signal input terminal.
Abstract translation: 提供一种移位寄存器单元，其包括正控制信号输入端，反向控制信号输入端，第一薄膜晶体管，第二薄膜晶体管，正输入端，反向输入端，上拉模块 以及第一复位模块，所述第一薄膜晶体管的栅极与所述正输入端子连接，所述第一薄膜晶体管的第一电极与所述正极控制信号输入端子连接，所述第一薄膜晶体管的第二电极 与所述上拉模块的上拉节点连接，所述第二薄膜晶体管的栅极与所述反向输入端子连接，所述第二薄膜晶体管的第一电极与所述第二薄膜晶体管的上拉节点连接， 上拉模块，第二薄膜晶体管的第二电极与反向控制信号输入端连接。
-
公开(公告)号：US11984094B2
公开(公告)日：2024-05-14
申请号：US18191628
申请日：2023-03-28
IPC: G09G3/36 , G02F1/1333 , G02F1/1343 , G02F1/1362 , H02M7/537 , H03F3/45
CPC classification number: G09G3/3696 , G02F1/133308 , G02F1/134345 , G02F1/136286 , H02M7/537 , H03F3/45475 , G09G2310/0243 , G09G2310/0291 , G09G2320/0252
Abstract: An array substrate has a display area and a bonding region. The display area includes a distal region, a proximal region, and a middle region therebetween. The array substrate includes a base, a common electrode located in the display area, a connecting lead disposed outside the distal region, a conductive frame at least partially surrounding the display area, and at least one first common signal line, at least one second common signal line and at least one third common signal line. The first common signal line, the second common signal line and the third common signal line are respectively coupled to portions of the common electrode located in the distal region, the proximal region and the middle region. The first common signal line is coupled to the connecting lead. The connecting lead and the portion of the common electrode located in the distal region are coupled to the conductive frame.
-
公开(公告)号：US11862060B2
公开(公告)日：2024-01-02
申请号：US17770415
申请日：2021-03-18
Inventor： Yan Yan , Xu Wang , Weitao Chen , Yu Ma , Zhiqiang Ma , Shunsha Lu
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0286 , G09G2320/02
Abstract: A shift register, a gate drive circuit and a display device. During forward scanning, the first input circuit supplies a signal of a first reference signal terminal to a first node in response to a signal of a first input signal terminal at an input phase, and the second input circuit supplies a signal of a second reference signal terminal to the first node in response to a signal of a second input signal terminal at a reset phase; and during reverse scanning, the second input circuit supplies the signal of the second reference signal terminal to the first node in response to the signal of the second input signal terminal at the input phase, and the first input circuit supplies the signal of the first reference signal terminal to the first node in response to the signal of the first input signal terminal at the reset phase.
-
公开(公告)号：US11295646B2
公开(公告)日：2022-04-05
申请号：US16073019
申请日：2017-11-21
Abstract: The present application discloses a shift-register circuit used as a shift-register unit of current stage including a control sub-circuit coupled to a shift-register unit of previous stage and configured to recharge a pull-up node of the shift-register unit of previous stage during a touch-control operation performed after a gate line scanning of previous stage ends and before the gate line scanning of current stage starts. The control sub-circuit is further configured to compensate an internal voltage of the shift-register unit of previous stage before the touch-control operation ends so that the shift-register unit of previous stage is triggered to perform the gate line scanning of previous stage followed by the shift-register unit of current stage to perform the gate line scanning of current stage.
-
-
-
-
-
-
-
-
-
Search Results
32
records
(took 0.019 seconds)
