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公开(公告)号：US12235553B2
公开(公告)日：2025-02-25
申请号：US17622205
申请日：2020-12-04
Inventor： Yanping Liao , Maoxiu Zhou , Yingmeng Miao , Haipeng Yang , Li Tian , Zhihua Sun
IPC: H01L27/12 , G02F1/1343 , G02F1/1362 , G02F1/1368
Abstract: An array substrate and a display panel are described. The array substrate may include a first base; a plurality of pixel units arrayed on the first base in a row direction and a column direction; each of the pixel units comprising at least two sub-pixels arranged in the row direction; a plurality of first scanning lines sequentially arranged on the first base in the column direction, at least one first scanning line being arranged at a side of each row of pixel units in the column direction, the first scanning lines being connected with the sub-pixels; and a plurality of second scanning lines sequentially arranged on the first base in the row direction, at least one second scanning line being arranged at a side of each column of pixel units in the row direction.
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公开(公告)号：US12222617B2
公开(公告)日：2025-02-11
申请号：US17441304
申请日：2021-02-02
Inventor： Jianhua Huang , Chongyang Zhao , Zhihua Sun , Yingmeng Miao , Yingying Qu
IPC: G02F1/1362 , G02F1/1368
Abstract: The present disclosure relates to the field of display technology, and in particular, to an array substrate and a display apparatus. The array substrate has a display area and a peripheral wiring area provided at at least one side of the display area. The display area includes a thin film transistor and a common electrode formed on the base substrate; the peripheral wiring area includes a first lead, a gate signal line and a common signal line formed on the base substrate; the first lead and the gate electrode of the thin film transistor are arranged in an identical layer and are electrically connected; the gate signal line is located on a side of the first lead away from the base substrate, and is electrically connected to the first lead through a first transition structure.
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公开(公告)号：US12087204B2
公开(公告)日：2024-09-10
申请号：US17912952
申请日：2021-10-28
Inventor： Xibin Shao , Yanping Liao , Dongchuan Chen , Yingmeng Miao , Shulin Yao , Yinlong Zhang , Qiujie Su , Jiantao Liu
IPC: G09G3/20
CPC classification number: G09G3/2092 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/041
Abstract: A display panel and a display device are disclosed. The display panel includes a gate driving circuit, a plurality of clock signal lines, a timing controller and a plurality of anti-cross-row circuits; the timing controller is configured to provide a first clock signal; the plurality of anti-cross-row circuits are connected with the timing controller and the plurality of clock signal lines, and are configured to adjust the first clock signal provided by the timing controller to a second clock signal, and output the second clock signal to the plurality of clock signal lines, and a falling duration of a falling edge of the second clock signal is less than a falling duration of a falling edge of the first clock signal; and each of the plurality of anti-cross-row circuits comprises at least one resistor and at least one inductor.
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公开(公告)号：US12014695B2
公开(公告)日：2024-06-18
申请号：US17633008
申请日：2021-04-09
Inventor： Dongchuan Chen , Yanping Liao , Yingmeng Miao , Yinlong Zhang , Shulin Yao , Xibin Shao , Seungmin Lee , Jiantao Liu
IPC: G09G3/36
CPC classification number: G09G3/3614 , G09G2310/0205 , G09G2310/0213 , G09G2310/0251 , G09G2310/08 , G09G2320/0257 , G09G2340/0435
Abstract: A display driving method, a display driving device and a display device are provided. The display driving method includes: when displaying an odd-numbered frame, providing first parity row data of the odd-numbered frame to a display array, to enable a third parity row of the display array to be displayed based on real data of the first parity row data and enable a fourth parity row of the display array to be displayed based on interpolation data of the first parity row data; and when displaying an even-numbered frame, providing second parity row data of the even-numbered frame to the display array, to enable the fourth parity row of the display array to be displayed based on real data of the second parity row data and enable the third parity row of the display array to be displayed based on interpolation data of the second parity row data.
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公开(公告)号：US20230401987A1
公开(公告)日：2023-12-14
申请号：US18457637
申请日：2023-08-29
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/08 , G09G2310/0286
Abstract: A gate driving circuit is provided, including N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where 1≤k≤K≤N; and an input signal terminal of a n-th stage is connected to an output signal terminal of a (n−i)-th stage, and reset signal terminals of the n-th and (n+1)-th stages are connected to an output signal terminal of a (n+j)-th stage, where 1
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Patent Agency Ranking
公开(公告)号：US12197669B2
公开(公告)日：2025-01-14
申请号：US18489747
申请日：2023-10-18
Inventor： Qiujie Su , Yanping Liao , Yingmeng Miao , Chongyang Zhao , Bo Hu , Xiaofeng Yin
IPC: G06F3/041 , G02F1/1333 , G02F1/1343 , G02F1/1362 , H01L27/12 , G06F3/044
Abstract: An array substrate and a touch display device are provided. In the array substrate, a first control unit and a second control unit are arranged opposite to each other in a first direction. A plurality of touch sensor blocks includes a first group of electrode blocks and a second group of electrode blocks arranged in the first direction, and a plurality of touch signal lines includes a first group of touch signal lines and a second group of touch signal lines arranged in the first direction. The touch signal lines in the first group of touch signal lines are coupled to the touch sensor blocks in the first group of electrode blocks respectively; and the touch signal lines in the second group of touch signal lines are coupled to the touch sensor blocks in the second group of electrode blocks respectively.
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公开(公告)号：US12112673B2
公开(公告)日：2024-10-08
申请号：US17796660
申请日：2021-06-10
Inventor： Chongyang Zhao , Yingmeng Miao , Zhihua Sun , Feng Qu , Xiaochun Xu
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0202 , G09G2310/0286
Abstract: The present disclosure provides a display panel and a display device. The display panel includes p pixel unit groups, and each of the p pixel unit groups includes q rows of pixel units, both p and q being integers greater than or equal to 2. Pixel units in a same group are simultaneously supplied with a gate scan signal by a same shift register, and pixel units in a same group and in a same column are supplied with data voltage signals through different data lines, respectively.
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公开(公告)号：US12034013B2
公开(公告)日：2024-07-09
申请号：US17594832
申请日：2020-12-21
Inventor： Chongyang Zhao , Yingmeng Miao , Zhihua Sun , Feng Qu , Xiaochun Xu
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/1244 , G02F1/136286 , G02F1/13625 , G02F1/136295 , G02F1/1368 , H01L27/1288
Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.
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公开(公告)号：US11955491B2
公开(公告)日：2024-04-09
申请号：US16965739
申请日：2019-09-29
Inventor： Yingmeng Miao , Yinshu Zhang , Zhihua Sun
IPC: H01L31/00 , G02F1/1333 , G02F1/1343 , G02F1/1362 , G02F1/1368 , H01L27/12 , G02F1/1345
CPC classification number: H01L27/124 , G02F1/133351 , G02F1/134309 , G02F1/136227 , G02F1/136286 , G02F1/1368 , H01L27/1292 , G02F1/13452
Abstract: An array substrate and a manufacturing method thereof, a motherboard and a display device are disclosed. The array substrate has a display region and a non-display region, and includes a base substrate, and a plurality of signal lines and at least one transfer electrode that are on the base substrate. The plurality of signal lines extend from the display region to the non-display region along a first direction, at least one of the plurality of signal lines includes a first trace in the display region and a second trace in the non-display region, the second trace includes at least two sub-traces disconnected from each other, a sub-trace, close to the display region, of the at least two sub-traces of the second trace is directly connected with the first trace, and every two adjacent sub-traces of the second trace are electrically connected with each other.
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公开(公告)号：US11783744B2
公开(公告)日：2023-10-10
申请号：US17445810
申请日：2021-08-24
Inventor： Qiujie Su , Zhihua Sun , Yingmeng Miao , Yinlong Zhang , Feng Qu , Seungmin Lee , Yanping Liao , Xibin Shao
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2310/0286 , G09G2310/08
Abstract: A gate driving circuit, a method for driving the gate driving circuit, and a display panel. The gate driving circuit includes N-stages of cascaded shift registers divided into at least one group of K-stages in which a clock signal terminal of a k-th stage of shift register is connected to receive a k-th clock signal, where N, k and K are positive integers, and 1≤k≤K≤N; and an input signal terminal of a n-th stage of shift register is connected to an output signal terminal of a (n−i)-th stage of shift register, and reset signal terminals of the n-th and (n+1)-th stages of shift registers are connected to an output signal terminal of a (n+j)-th stage of shift register, wherein the n is one of an odd number and an even number, where i and j are positive integers, 1
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