公开(公告)号：US20100318781A1

公开(公告)日：2010-12-16

申请号：US12864589

申请日：2009-01-29

申请人： Kenneth Alexander Nicolson ,  Hideki Matsushima ,  Hisashi Takayama ,  Takayuki Ito ,  Tomoyuki Haga

发明人： Kenneth Alexander Nicolson ,  Hideki Matsushima ,  Hisashi Takayama ,  Takayuki Ito ,  Tomoyuki Haga

IPC分类号： G06F21/00 ,  G06F9/00

CPC分类号： G06F21/575

摘要： A method to allow a device to boot in a secure fashion, even though some of the components within the secure device's firmware may not be present, not correctly authorized, or not correctly operating.

摘要翻译： 即使安全设备的固件中的某些组件可能不存在，未正确授权或不正确操作，允许设备以安全方式引导的方法。

公开(公告)号：US07849331B2

公开(公告)日：2010-12-07

申请号：US12081889

申请日：2008-04-23

申请人： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

发明人： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC分类号： G06F21/00

CPC分类号： G06F21/123 ,  G06F21/572 ,  G06F21/72

摘要： A system including a secure LSI 1 establishes a communication path to/from a server 3 (UD1), and receives a common key-encrypted program generated by encryption with a common key and transmitted from the server 3 (UD6 and UD7). The received common key-encrypted program is decrypted to generate a raw program, and the raw program is re-encrypted with an inherent key to newly generate an inherent key-encrypted program, which is stored in an external memory.

摘要翻译： 包括安全LSI1的系统建立到服务器3（UD1）的通信路径，并且从服务器3（UD6和UD7）接收通过公共密钥通过加密生成的公共密钥加密程序。 对所接收的公用密钥加密程序进行解密以生成原始程序，并且用固有密钥重新加密原始程序，以新生成存储在外部存储器中的固有密钥加密程序。

公开(公告)号：US07781848B2

公开(公告)日：2010-08-24

申请号：US11704924

申请日：2007-02-12

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US20100193874A1

公开(公告)日：2010-08-05

申请号：US12757658

申请日：2010-04-09

申请人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

发明人： Takayuki Ito ,  Kyoichi Suguro ,  Kouji Matsuo

IPC分类号： H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823814 ,  H01L21/823842

摘要： A semiconductor device includes a semiconductor region, a source region, a drain region, a source extension region a drain extension region, a first gate insulation film, a second gate insulation film, and a gate electrode. The source region, drain region, source extension region and drain extension region are formed in a surface portion of the semiconductor region. The first gate insulation film is formed on the semiconductor region between the source extension region and the drain extension region. The first gate insulation film is formed of a silicon oxide film or a silicon oxynitride film having a nitrogen concentration of 15 atomic % or less. The second gate insulation film is formed on the first gate insulation film and contains nitrogen at a concentration of between 20 atomic % and 57 atomic %. The gate electrode is formed on the second gate insulation film.

摘要翻译： 半导体器件包括半导体区域，源极区域，漏极区域，源极延伸区域，漏极延伸区域，第一栅极绝缘膜，第二栅极绝缘膜和栅极电极。 源极区域，漏极区域，源极延伸区域和漏极延伸区域形成在半导体区域的表面部分中。 第一栅极绝缘膜形成在源极延伸区域和漏极延伸区域之间的半导体区域上。 第一栅极绝缘膜由氮浓度为15原子％以下的氧化硅膜或氮氧化硅膜形成。 第二栅极绝缘膜形成在第一栅极绝缘膜上，并且含有浓度为20原子％至57原子％之间的氮。 栅电极形成在第二栅绝缘膜上。

公开(公告)号：US07746207B2

公开(公告)日：2010-06-29

申请号：US10571771

申请日：2004-11-05

申请人： Mitsuhiro Yamashita ,  Takashi Nagasaka ,  Hideki Miura ,  Yasuhiro Matsukawa ,  Kazuo Sato ,  Akira Sato ,  Hironori Sato ,  Takayuki Ito ,  Yasuhiko Kitajima

发明人： Mitsuhiro Yamashita ,  Takashi Nagasaka ,  Hideki Miura ,  Yasuhiro Matsukawa ,  Kazuo Sato ,  Akira Sato ,  Hironori Sato ,  Takayuki Ito ,  Yasuhiko Kitajima

IPC分类号： H01F5/00

CPC分类号： H01F27/292 ,  H01F17/045 ,  H01F27/027 ,  H01F27/33 ,  H01F41/082

摘要： A coil apparatus having a divided winding conformation and a manufacturing method of the coil apparatus which can prevent a winding from collapsing while achieving a reduction in size of a core and simplification of a structure. A coil apparatus includes a ferrite core and a coil provided around the core. The coil includes at least a first coil portion and a second coil portion, and a boundary end surface of the first coil portion on the second coil portion side is inclined in such a manner that its inner peripheral side is closer to the second coil portion than its outer peripheral side. Further, a boundary end surface of the second coil portion on the first coil portion side is inclined in such a manner that its outer peripheral side is closer to the first coil portion than its inner peripheral side.

摘要翻译： 具有分割绕组结构的线圈装置和线圈装置的制造方法，其可以防止绕组塌陷同时实现芯的尺寸的减小并且简化结构。 线圈装置包括铁氧体磁芯和设置在磁芯周围的线圈。 线圈至少包括第一线圈部分和第二线圈部分，并且第二线圈部分侧的第一线圈部分的边界端面以其内周侧比第二线圈部分更靠近第二线圈部分的方式倾斜， 其外围边。 此外，第一线圈部分侧的第二线圈部分的边界端面以其外周侧比其内周侧更靠近第一线圈部分的方式倾斜。

公开(公告)号：US07685435B2

公开(公告)日：2010-03-23

申请号：US10624481

申请日：2003-07-23

申请人： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

发明人： Makoto Fujiwara ,  Yusuke Nemoto ,  Junichi Yasui ,  Takuji Maeda ,  Takayuki Ito ,  Yasushi Yamada ,  Shinji Inoue

IPC分类号： G06F11/30

CPC分类号： G06F21/72 ,  G06F8/60 ,  G06F21/575 ,  G06F2221/2105

摘要： An development environment of a high security level is provided for a key-installed system. Development of a program for a system having an LSI device which includes a secure memory is performed by providing another LSI device having the same structure and setting the provided LSI device to a development mode which is different from a product operation mode. Alternatively, the provided LSI device is set to an administrator mode to perform development and encryption of a key-generation program. The LSI device is set to a key-generation mode to execute the encrypted key-generation program, thereby generating various keys.

摘要翻译： 为安装密钥的系统提供了高安全级别的开发环境。 通过提供具有相同结构的另一LSI器件和将所提供的LSI器件设置为与产品操作模式不同的开发模式来执行具有包括安全存储器的LSI器件的系统的程序的开发。 或者，将所提供的LSI设备设置为管理员模式，以执行密钥生成程序的开发和加密。 LSI设备被设置为执行加密密钥生成程序的密钥生成模式，从而生成各种密钥。

公开(公告)号：US07501332B2

公开(公告)日：2009-03-10

申请号：US11097259

申请日：2005-04-04

申请人： Takayuki Ito ,  Kyoichi Suguro

发明人： Takayuki Ito ,  Kyoichi Suguro

IPC分类号： H01L21/425

CPC分类号： H01L21/2236 ,  H01L21/823814 ,  Y10S438/918 ,  Y10S438/964

摘要： A doping method includes implanting first impurity ions into a semiconductor substrate, so as to form a damaged region in the vicinity of a surface of the semiconductor substrate, the first impurity ions not contributing to electric conductivity; implanting second impurity ions into the semiconductor substrate through the damaged region, the second impurity ions having an atomic weight larger than the first impurity ions and contributing to the electric conductivity; and heating the surface of the semiconductor substrate with a light having a pulse width of about 0.1 ms to about 100 ms, so as to activate the second impurity ions.

摘要翻译： 掺杂方法包括将第一杂质离子注入到半导体衬底中，以在半导体衬底的表面附近形成损伤区域，不对导电性有贡献的第一杂质离子; 通过损伤区域将第二杂质离子注入到半导体衬底中，第二杂质离子的原子量大于第一杂质离子并有助于导电性; 并用脉冲宽度为约0.1ms至约100ms的光来加热半导体衬底的表面，以激活第二杂质离子。

公开(公告)号：US20090026178A1

公开(公告)日：2009-01-29

申请号：US12232443

申请日：2008-09-17

申请人： Takayuki Ito

发明人： Takayuki Ito

IPC分类号： B23K26/00

CPC分类号： H01L21/67115 ,  H01L21/324 ,  H01L21/67103

摘要： An apparatus for annealing a substrate includes a substrate stage having a substrate mounting portion configured to mount the substrate; a heat source having a plurality of heaters disposed under the substrate mounting portion, the heaters individually preheating a plurality areas defined laterally in the substrate through a bottom surface of the substrate; and a light source facing a top surface of the substrate, configured to irradiate a pulsed light at a pulse width of about 0.1 ms to about 100 ms on the entire top surface of the substrate.

摘要翻译： 用于退火衬底的设备包括：衬底台，其具有被配置为安装衬底的衬底安装部; 热源，其具有设置在所述基板安装部下方的多个加热器，所述加热器通过所述基板的底面单独地预热在所述基板中横向限定的多个区域; 以及面向衬底的顶表面的光源，被配置为在衬底的整个顶表面上以约0.1ms至约100ms的脉冲宽度照射脉冲光。

公开(公告)号：US20090013196A1

公开(公告)日：2009-01-08

申请号：US12160281

申请日：2007-02-02

申请人： Takayuki Ito ,  Yoshikatsu Ito

发明人： Takayuki Ito ,  Yoshikatsu Ito

IPC分类号： H04L9/06 ,  G06F1/26 ,  G06F21/00

CPC分类号： H04L9/3236 ,  H04L2209/603

摘要： A secure processing device having a power saving mode, which is used for built-in apparatuses, calculates a hash value of secure data that needs to be saved when switching to the power saving mode, stores the calculated hash value in a protection storage unit whose data is not lost even in the power saving mode, encrypts the secure data and stores the encrypted data in an external memory when switching to the power saving mode. When switching back to the normal power mode, the secure processing device decrypts the encrypted data, calculates a hash value of the decrypted data and compares the hash value with the hash value stored in the protection storage unit. The decrypted data is restored to the protection storage unit when the hash values are identical, but discarded together with the encrypted data stored in the external memory when the hash values are not identical.

摘要翻译： 具有省电模式的安全处理装置，用于内置装置，计算切换到省电模式时需要保存的安全数据的哈希值，将计算出的散列值存储在保护存储部中， 即使在省电模式下数据也不会丢失，在切换到省电模式时，加密安全数据并将加密数据存储在外部存储器中。 当切换回正常功率模式时，安全处理装置解密加密数据，计算解密数据的散列值，并将哈希值与存储在保护存储单元中的散列值进行比较。 当哈希值相同时，解密的数据被恢复到保护存储单元，但是当哈希值不相同时，被解密的数据与存储在外部存储器中的加密数据一起被丢弃。

公开(公告)号：US20080102574A1

公开(公告)日：2008-05-01

申请号：US11923467

申请日：2007-10-24

申请人： Takayuki Ito

发明人： Takayuki Ito

IPC分类号： H01L21/8238

CPC分类号： H01L21/823814 ,  H01L21/268 ,  H01L21/324 ,  H01L29/6653

摘要： A manufacturing method of a CMOS semiconductor device includes using, in an nMOS, spike RTA (first annealing) together with ultra-rapid rising/falling temperature annealing (second annealing) whose temperature increase/decrease rate is higher than that of the spike RTA, and applying the ultra-rapid rising/falling temperature annealing (second annealing) alone in a pMOS, when activating a shallow source/drain extension region.

摘要翻译： CMOS半导体器件的制造方法包括在nMOS中使用峰值RTA（第一退火）以及其升温/降温速率高于尖峰RTA的超快速上升/下降温度退火（第二退火） 并且当激活浅源极/漏极延伸区域时，在pMOS中单独应用超快速上升/下降温度退火（第二退火）。