公开(公告)号：US20070258552A1

公开(公告)日：2007-11-08

申请号：US11742577

申请日：2007-04-30

申请人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

发明人： Martin Streibl ,  Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz

IPC分类号： H04L7/00

CPC分类号： H04L7/0054 ,  G11C7/1078 ,  G11C7/1084 ,  H03L7/08 ,  H04L7/007

摘要： A data receiver has a sampling unit connected to a data signal input and configured to sample a data signal amplitude and amplify the sampled data signal amplitude to a predetermined value, a sampling clock generator unit connected to the sampling unit and configured to predetermine a sampling clock for the sampling unit, an evaluation unit connected to the sampling unit and configured to determine the time duration required by the sampling unit for amplifying the sampled data signal amplitude to the predetermined value and evaluate the time duration determined, and a control unit connected to the evaluation unit and the sampling clock generator and configured to define the sampling clock on the basis of the evaluation of the time duration determined by the evaluation unit.

摘要翻译： 数据接收机具有连接到数据信号输入端并被配置为采样数据信号振幅并将采样数据信号振幅放大到预定值的采样单元，采样时钟发生器单元连接到采样单元并被配置为预先确定采样时钟 对于采样单元，评估单元连接到采样单元并且被配置为确定采样单元需要的持续时间以将采样的数据信号幅度放大到预定值并评估所确定的持续时间，以及控制单元 评估单元和采样时钟发生器，并且被配置为基于由评估单元确定的持续时间的评估来定义采样时钟。

公开(公告)号：US07290022B2

公开(公告)日：2007-10-30

申请号：US10714811

申请日：2003-11-17

申请人： Heinz Mattes ,  Peter Gregorius ,  Paul Georg Lindt

发明人： Heinz Mattes ,  Peter Gregorius ,  Paul Georg Lindt

IPC分类号： G06F17/10

CPC分类号： H03H17/0223 ,  H03H17/04

摘要： A method and apparatus for fast digital filtering that requires only filter stages of first and second order. A desired rational filter transfer function is represented as a sum of first and second order intermediate transfer functions. A time dependent input signal is first fed in parallel into a plurality of first and second order intermediate recursive filter stages. Then, the outputs of the intermediate filter stages are summed up to an output filter signal that corresponds to the desired rational filter transfer function. The method and apparatus reduces the amount of calculational effort to the order of O(N), where N denotes the number of sampling points in the time domain, because the digital filtering is based on a discrete recursive convolution in the time domain.

摘要翻译： 用于快速数字滤波的方法和装置，其仅需要一阶和二阶滤波器阶段。 期望的合理滤波传递函数被表示为第一和第二阶中间传递函数的和。 首先将依赖于时间的输入信号并入多个第一和第二阶中间递归滤波器级。 然后，将中间滤波器级的输出相加到对应于期望的有理滤波器传递函数的输出滤波器信号。 该方法和装置将计算努力的量减少到O（N）的阶数，其中N表示时域中的采样点的数量，因为数字滤波是基于时域中的离散递归卷积。

公开(公告)号：US07215597B2

公开(公告)日：2007-05-08

申请号：US11046160

申请日：2005-01-28

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093

摘要： One embodiment of the present invention provides a memory device comprising an array of memory cells, a control logic for writing data to and reading data from the array of memory cells, the control logic comprising a first interface, an input/output section for exchanging data, address and control signals with a circuit external to the memory device, the input/output section comprising a second interface for sending signals to and receiving signals from the first interface of the control logic, and a synchronizing facility connected to the first interface of the control logic and to the second interface of the input/output section for synchronizing the first interface of the control logic and the second interface of the input/output section.

摘要翻译： 本发明的一个实施例提供了一种存储器件，包括存储器单元阵列，用于将数据写入存储器单元阵列并从存储器单元阵列读取数据的控制逻辑，该控制逻辑包括第一接口，用于交换数据的输入/输出部分 ，具有存储器件外部电路的地址和控制信号，所述输入/输出部分包括用于向控制逻辑的第一接口发送信号并从其接收信号的第二接口，以及连接到控制逻辑的第一接口的同步设备 控制逻辑和输入/输出部分的第二接口，用于使控制逻辑的第一接口和输入/输出部分的第二接口同步。

公开(公告)号：US07212038B2

公开(公告)日：2007-05-01

申请号：US10485336

申请日：2002-07-25

申请人： Peter Gregorius ,  Armin Hanneberg ,  Peter Laaser

发明人： Peter Gregorius ,  Armin Hanneberg ,  Peter Laaser

IPC分类号： H03K19/094

CPC分类号： H04L25/028 ,  H04L25/0272 ,  H04L25/0292

摘要： A line driver (3) for transmitting data with high bit rates, in particular for wire-bound data transmission in the full-duplex process, comprises a differential pair with differential pair transistors (14, 15) for generating transmission impulses as a function of the data to be transmitted, whereby the transmission impulses are preferably output via cascode transistors (16, 17), each with the differential pair transistors (14, 15) forming a cascode circuit, onto the data transmission line (8, 9) connected to the line driver (3). For reproducing the behaviour of the differential pair a replica differential pair with replica differential pair transistors (18, 19) is provided, generating replica impulses corresponding to the transmission impulses, which replica impulses can be fed via replica cascode transistors (20, 21) to a hybrid integrated circuit (6) for effecting echo compensation in relation to impulses received via the data transmission line (8, 9)

摘要翻译： 用于以高比特率发送数据的线路驱动器（3），特别是用于全双工过程中用于有线数据传输的线路驱动器（3）包括与差分对晶体管（14,15）的差分对，用于产生传输脉冲作为 要发送的数据，由此传输脉冲优选地通过共模共轭二极管（16,17）输出，每个都具有形成共源共栅电路的差分对晶体管（14,15）到与数据传输线（8,9）相连的数据传输线 线路驱动器（3）。 为了再现差分对的行为，提供了具有复制差分对晶体管（18,19）的复制差分对，产生对应于传输脉冲的复制脉冲，该复制脉冲可以经由复制共源共栅晶体管（20,21）馈送到 用于对通过数据传输线（8,9）接收的脉冲进行回波补偿的混合集成电路（6）

公开(公告)号：US07184502B2

公开(公告)日：2007-02-27

申请号：US10301444

申请日：2002-11-21

申请人： Bernard Engl ,  Peter Gregorius

发明人： Bernard Engl ,  Peter Gregorius

IPC分类号： H04L7/00 ,  H03K5/01

CPC分类号： H04L7/0054 ,  H03L7/07 ,  H03L7/091 ,  H03L7/0998 ,  H04L7/0334

摘要： A circuit arrangement to recover clock and data from a received signal comprises an electronic commutator for sampling the received signal in such a way that several sampling values of a bit cell transmitted with the received signal are distributed time-wise one after the other onto several output connections of the commutator device and emitted there in the form of corresponding intermediate signals. A first circuit combines a first group of intermediate signals of the commutator device into a first uniting signal, which serves as the basis for data recovery or comprises the recovered data signal, while a second circuit combines a second group of intermediate signals of the commutator device into a second uniting signal, which serves as the basis for clock recovery. The second uniting signal is fed to a phase regulator arrangement, which, dependent on this, sets the sampling phases assigned to the individual output connections of the commutator device.

摘要翻译： 从接收信号中恢复时钟和数据的电路装置包括一个电子换向器，用于对接收到的信号进行采样，使得用接收信号发送的位单元的几个采样值在时间上逐个分配到多个输出 换向器装置的连接并以对应的中间信号的形式发射到那里。 第一电路将换向器装置的第一组中间信号组合成第一联合信号，其作为数据恢复的基础或包括恢复的数据信号，而第二电路组合换向器装置的第二组中间信号 成为第二个组合信号，作为时钟恢复的基础。 第二组合信号被馈送到相位调节器装置，相位调节器装置根据此设置分配给换向器装置的各个输出连接的采样相位。

公开(公告)号：US20070005831A1

公开(公告)日：2007-01-04

申请号：US11171110

申请日：2005-06-30

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G06F5/00 ,  G06F3/00

CPC分类号： G06F13/4243

摘要： The present invention relates to a semiconductor memory system including a memory controller transmitting high speed write data, command and address signal streams based on a predefined transmission protocol and a high speed write clock signal and for receiving serial high speed read data signals as signal frames based on the transmission protocol and a memory module which includes a plurality of semiconductor memory chips and a smart buffer chip which is different from prior art register chips because it forms a genuine high speed serial link including the complete digital function thereof such as protocol layer, error coding and so on. The smart buffer chip communicates with the memory chips by a low speed interface and through low speed point-to-point or fly-by connection lines.

摘要翻译： 本发明涉及一种包括存储器控制器的半导体存储器系统，存储器控制器基于预定义的传输协议和高速写入时钟信号传输高速写入数据，命令和地址信号流，并且用于接收作为信号帧的串行高速读取数据信号 在传输协议和包括多个半导体存储器芯片的存储器模块和与现有技术寄存器芯片不同的智能缓冲器芯片，因为它形成了包括其完整的数字功能的真正的高速串行链路，例如协议层，错误 编码等。 智能缓冲芯片通过低速接口和低速点对点或飞越连接线路与存储器芯片进行通信。

公开(公告)号：US20060050830A1

公开(公告)日：2006-03-09

申请号：US11194770

申请日：2005-08-01

申请人： Nicola Da Dalt ,  Peter Gregorius

发明人： Nicola Da Dalt ,  Peter Gregorius

IPC分类号： H03D3/24

CPC分类号： H03L7/099 ,  H03C3/095 ,  H03L7/087 ,  H03L7/093 ,  H03L2207/50

摘要： A method and a device for generating a clock signal (Fout) are provided, wherein a digital phase difference signal (X) is formed depending on a phase difference between a reference clock signal (Fin) and a feedback signal (Ffb) derived from the clock signal (Fout) and wherein the digital phase difference signal (X) is digitally filtered, in order to form a digital filtered phase difference signal (U). A digitally controlled oscillator (5) is activated by a digital control signal dependent on the digital filtered phase difference signal (U) to generate the clock signal (Fout). With a device of this kind clock signals with frequencies in the gigahertz range can be generated with a minimum of analog circuit parts.

摘要翻译： 提供了一种用于产生时钟信号（F OUT）的方法和装置，其中根据参考时钟信号（F SUB）之间的相位差形成数字相位差信号（X） 并且其中数字相位差信号（X）被数字滤波，并且其中数字相位差信号（X）被<！ - SIPO - ，以形成数字滤波相位差信号（U）。 数字控制振荡器（5）由取决于数字滤波相位差信号（U）的数字控制信号激活，以产生时钟信号（F OUT）。 使用这种类型的器件，可以使用最小的模拟电路部分来生成千兆赫兹范围内的频率的时钟信号。

公开(公告)号：US06700361B2

公开(公告)日：2004-03-02

申请号：US10131375

申请日：2002-04-24

申请人： Peter Gregorius

发明人： Peter Gregorius

IPC分类号： G05F140

CPC分类号： G05F1/575 ,  G05F3/262

摘要： A voltage regulator is described, the output voltage of which depends on a drive to a transistor contained in the voltage regulator. The voltage regulator described is distinguished by the fact that it contains a stabilization circuit that can change the current flowing through the transistor. Such a voltage regulator is simple to configure and to implement and, with minimum intrinsic power requirement, is stable under all circumstances.

摘要翻译： 描述了一种电压调节器，其输出电压取决于包含在电压调节器中的晶体管的驱动。 所描述的电压调节器的特征在于它包含可以改变流过晶体管的电流的稳定电路。 这种电压调节器易于配置和实现，并且具有最小内在功率要求，在所有情况下都是稳定的。

公开(公告)号：US08392779B2

公开(公告)日：2013-03-05

申请号：US12109826

申请日：2008-04-25

申请人： Andreas Schneider ,  Markus Balb ,  Thomas Hein ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Michael Richter

发明人： Andreas Schneider ,  Markus Balb ,  Thomas Hein ,  Christoph Bilger ,  Martin Brox ,  Peter Gregorius ,  Michael Richter

IPC分类号： G06F11/00 ,  G06F11/30 ,  G08C25/00 ,  H03M13/00

CPC分类号： G11C29/021 ,  G06F11/1004 ,  G11C7/1006 ,  G11C11/401 ,  G11C11/4074 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0411 ,  H03M13/03

摘要： A method of adjusting an interface voltage includes transferring data between a memory device and a controller, and detecting whether an error occurred in the transfer of data. An interface voltage of at least one of the memory device and the controller is adjusted based on the detection.

摘要翻译： 调整接口电压的方法包括在存储器件和控制器之间传输数据，以及检测数据传输中是否发生错误。 基于检测来调整存储器件和控制器中的至少一个的接口电压。

公开(公告)号：US07817766B2

公开(公告)日：2010-10-19

申请号：US11554554

申请日：2006-10-30

申请人： Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz ,  Martin Streibl

发明人： Peter Gregorius ,  Thomas Rickes ,  Ralf Schledz ,  Martin Streibl

IPC分类号： H03D3/24

CPC分类号： H03L7/0814 ,  H03L7/0805

摘要： A digital control loop and a method for clock generation. A control loop includes at least one phase detector configured to detect a phase shift of a feedback signal relative to a reference clock signal and output a correction signal on the basis of the phase shift detected. At least one control loop filter is configured to output, on the basis of the correction signal, a first control signal and a second control signal, the first control signal being substantially the same as the second control signal except that oscillations are suppressed in the second control signal. At least one first phase generator is configured to output a first clock signal on the basis of the first control signal and the first phase reference signal, wherein the first clock signal is transmitted at least partially as feedback signal to the phase detector. At least one second phase generator receives the second control signal and the first phase reference signal, wherein the second phase generator is functionally substantially the same as the first phase generator and is configured to output a second clock signal on the basis of the second control signal and the first phase reference signal.

摘要翻译： 数字控制回路和时钟生成方法。 控制回路包括至少一个相位检测器，被配置为检测反馈信号相对于参考时钟信号的相移，并且基于检测到的相移输出校正信号。 至少一个控制环路滤波器被配置为基于校正信号输出第一控制信号和第二控制信号，第一控制信号基本上与第二控制信号相同，除了在第二控制信号中振荡被抑制 控制信号。 至少一个第一相位发生器被配置为基于第一控制信号和第一相位参考信号来输出第一时钟信号，其中第一时钟信号至少部分地作为反馈信号发送到相位检测器。 至少一个第二相位发生器接收第二控制信号和第一相位参考信号，其中第二相位发生器在功能上基本上与第一相位发生器相同，并且被配置为基于第二控制信号输出第二时钟信号 和第一相位参考信号。