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    Memory devices and methods which may facilitate tensor memory access
    101.
    发明授权
    Memory devices and methods which may facilitate tensor memory access 有权

    公开(公告)号：US12229044B2

    公开(公告)日：2025-02-18

    申请号：US17888748

    申请日：2022-08-16

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Jaime Cummins ,  Tamara Schmitz ,  Jeremy Chritz

    IPC: G06F12/02 ,  G06F12/06 ,  G06F12/0864 ,  G06F12/0893

    Abstract: Methods, apparatuses, and systems for tensor memory access are described. Multiple data located in different physical addresses of memory may be concurrently read or written by, for example, employing various processing patterns of tensor or matrix related computations. A memory controller, which may comprise a data address generator, may be configured to generate a sequence of memory addresses for a memory access operation based on a starting address and a dimension of a tensor or matrix. At least one dimension of a tensor or matrix may correspond to a row, a column, a diagonal, a determinant, or an Nth dimension of the tensor or matrix. The memory controller may also comprise a buffer configured to read and write the data generated from or according to a sequence of memory of addresses.

    COOPERATIVE LEARNING NEURAL NETWORKS AND SYSTEMS
    102.
    发明公开
    COOPERATIVE LEARNING NEURAL NETWORKS AND SYSTEMS 审中-公开

    公开(公告)号：US20240256869A1

    公开(公告)日：2024-08-01

    申请号：US18609221

    申请日：2024-03-19

    Applicant: Micron Technology, Inc.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: G06N3/08 ,  G06N3/04 ,  G06N3/045 ,  H04W4/02 ,  H04W4/38 ,  H04W4/40 ,  H04W4/90

    CPC classification number: G06N3/08 ,  G06N3/04 ,  G06N3/045 ,  H04W4/02 ,  H04W4/023 ,  H04W4/38 ,  H04W4/40 ,  H04W4/90

    Abstract: Systems, methods, and apparatuses related to cooperative learning neural networks are described. Cooperative learning neural networks may include neural networks which utilize sensor data received wirelessly from at least one other wireless communication device to train the neural network. For example, cooperative learning neural networks described herein may be used to develop weights which are associated with objects or conditions at one device and which may be transmitted to a second device, where they may be used to train the second device to react to such objects or conditions. The disclosed features may be used in various contexts, including machine-type communication, machine-to-machine communication, device-to-device communication, and the like. The disclosed techniques may be employed in a wireless (e.g., cellular) communication system, which may operate according to various standardized protocols.

    Methods and Apparatus for Probabilistic Refresh in Volatile Memory Devices
    103.
    发明公开
    Methods and Apparatus for Probabilistic Refresh in Volatile Memory Devices 审中-公开

    公开(公告)号：US20230410873A1

    公开(公告)日：2023-12-21

    申请号：US18456152

    申请日：2023-08-25

    Applicant: Micron Technology, Inc.

    Inventor： David Hulton ,  Jeremy Chritz ,  Jonathan D. Harms

    IPC: G11C11/406 ,  G06F11/07 ,  G06F16/2458 ,  G11C11/4096

    CPC classification number: G11C11/406 ,  G06F11/073 ,  G06F11/076 ,  G06F16/2465 ,  G11C11/4096 ,  G06F11/0787 ,  G06F2216/03 ,  G06Q20/0655

    Abstract: Methods and apparatus for utilizing non-traditional (e.g., probabilistic or statistically-based) refresh schemes in non-volatile memory. In one embodiment, the memory is characterized in terms of its performance, such as based on BER (bit error rate) as a function of refresh rate based on statistical data for decay of capacitance within the cells of the device with time. In one variant, error-tolerant applications make use of the non-traditionally refreshed (or unrefreshed) memory with enhanced memory bandwidth, since refresh operations have been reduced or eliminated. In another variant, an extant refresh scheme is modified based on a specified minimum allowable performance level for the memory device, In yet another embodiment, error-intolerant applications operate the memory with a reduced or eliminated refresh, and cells or regions of the memory not adequately refreshed by presumed random read/write operations of the memory over time are actively refreshed.

    TEMPERATURE CHANGE MEASUREMENT TO DETECT ATTACK
    104.
    发明公开
    TEMPERATURE CHANGE MEASUREMENT TO DETECT ATTACK 审中-公开

    公开(公告)号：US20230334152A1

    公开(公告)日：2023-10-19

    申请号：US17659409

    申请日：2022-04-15

    Applicant: Micron Technology, Inc.

    Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

    IPC: G06F21/55 ,  G01K3/00 ,  G01K1/02

    CPC classification number: G06F21/554 ,  G01K3/005 ,  G01K1/026

    Abstract: Methods, systems, and devices for temperature change measurement to detect an attack on a memory device are described. A memory device may measure a rate of change for temperature readings at a dynamic random access memory (DRAM) component of the memory device (e.g., using sensors at the DRAM component). The memory device may compare the rate of change for the temperature to a threshold, for example, using circuitry, a threshold value stored in memory, or both. If the memory device determines that the rate of change for the temperature satisfies the threshold, the memory device may disable one or more features of the memory device to protect against a potential attack. For example, an attack on the memory device may be indicated by the change in temperature readings at the DRAM component, and the memory device may perform one or more protective measures based on detecting the temperature change.

    VOLTAGE INPUT AND CLOCK SPEED CHANGE DETERMINATION TO DETECT ATTACK
    107.
    发明公开
    VOLTAGE INPUT AND CLOCK SPEED CHANGE DETERMINATION TO DETECT ATTACK 审中-公开

    公开(公告)号：US20230205874A1

    公开(公告)日：2023-06-29

    申请号：US17653265

    申请日：2022-03-02

    Applicant: Micron Technology, Inc.

    Inventor： Aaron P. Boehm ,  David Hulton ,  Jeremy Chritz ,  Tamara Schmitz ,  Max S. Vohra

    IPC: G06F21/55

    CPC classification number: G06F21/554 ,  G06F2221/034

    Abstract: Methods, systems, and devices for voltage input and clock speed change determination to detect an attack are described. In some systems, a memory device may receive first signaling indicative of a first value for an input (e.g., voltage input, clock speed) to the memory device. The memory device may further receive second signaling indicative of a second (e.g., time-delayed) value for the input to the memory device. The memory device may detect a change to the input based on the first signaling and the second signaling. For example, the memory device may compare the first signaling to the second signaling, may compare a difference between the first signaling and the second signaling to a threshold, or both. If the input changes (e.g., by a threshold amount), the memory device may disable one or more features to protect against an attack on the memory device.

    Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher
    109.
    发明授权
    Memory systems and devices including examples of accessing memory and generating access codes using an authenticated stream cipher 有权

    公开(公告)号：US11537298B2

    公开(公告)日：2022-12-27

    申请号：US17108904

    申请日：2020-12-01

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Jeremy Chritz ,  David Hulton

    IPC: G06F3/06 ,  G06F12/0877 ,  H04L9/06

    Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

    Apparatus and method to switch configurable logic units
    110.
    发明授权
    Apparatus and method to switch configurable logic units 有权

    公开(公告)号：US11507531B2

    公开(公告)日：2022-11-22

    申请号：US17184945

    申请日：2021-02-25

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Fa-Long Luo ,  Tamara Schmitz ,  Jeremy Chritz ,  Jaime Cummins

    IPC: G06F15/78 ,  G06F9/38

    Abstract: Examples described herein include systems and methods which include an apparatus comprising a plurality of configurable logic units and a plurality of switches, with each switch being coupled to at least one configurable logic unit of the plurality of configurable logic units. The apparatus further includes an instruction register configured to provide respective switch instructions of a plurality of switch instructions to each switch based on a computation to be implemented among the plurality of configurable logic units. For example, the switch instructions may include allocating the plurality of configurable logic units to perform the computation and activating an input of the switch and an output of the switch to couple at least a first configurable logic unit and a second configurable logic unit. In various embodiments, configurable logic units can include arithmetic logic units (ALUs), bit manipulation units (BMUs), and multiplier-accumulator units (MACs).

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