公开(公告)号：US20220188237A1

公开(公告)日：2022-06-16

申请号：US17122174

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Luca Porzio ,  Roberto Izzi ,  Jonathan S. Parry

IPC: G06F12/0873 ,  G06F12/0891 ,  G06F12/02 ,  G06F12/06

Abstract: Methods, systems, and devices for unmap operation techniques are described. A memory system may include a volatile memory device and a non-volatile memory device. The memory system may receive a set of unmap commands that each include a logical block address associated with unused data. The memory system may determine whether one or more parameters associated with the set of unmap commands satisfy a threshold. If the one or more parameters satisfy the threshold, the memory system may select a first procedure for performing the set of unmap commands different from a second procedure (e.g., a default procedure) for performing the set of unmap commands and may perform the set of unmap commands using the first procedure. If the one or more parameters do not satisfy the threshold, the memory system may perform the set of unmap commands using the second procedure.

公开(公告)号：US11164784B2

公开(公告)日：2021-11-02

申请号：US16548666

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: H01L21/82 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides, for each respective signal, driving a respective open-drain transistor to conduct, in which an output of each open-drain transistor connects to the common node and the common node connects to a reference voltage, to change a voltage of a common node corresponding to the respective signal; and utilizing the voltage of the common node to indicate total power consumption of the dice.

公开(公告)号：US11079829B2

公开(公告)日：2021-08-03

申请号：US16510696

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David A. Palmer

IPC: G06F1/00 ,  G06F1/3225 ,  G06F3/06 ,  G06F1/3234 ,  G06F13/16 ,  G06F1/30

Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each of a plurality of dice in the power network, a first activity state value indicating that the respective die is in a high current state, a second activity state value indicating that the respective die is a moderate current state, or a third activity state value indicating that the respective die is a low current state. The received activity state values include at least one second or third activity state value. The first die determines, using the received activity state values, a first sum of the activity state values. The first die further selects an activity state based upon the first sum and sends, to the plurality of dice, an activity state value corresponding to the selected activity state.

公开(公告)号：US11049565B2

公开(公告)日：2021-06-29

申请号：US15959868

申请日：2018-04-23

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C16/14 ,  G11C16/30 ,  G11C17/16 ,  G11C17/18 ,  G11C16/22 ,  G11C13/00 ,  G11C11/16 ,  G11C11/22 ,  G11C16/08

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as a volatile memory by erasing or degrading data in the event of a changed power condition such as a power-loss event, a power-off event, or a power-on event. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to detect a changed power condition of the memory device, and to erase or degrade data at the one or more addresses in response to detecting the changed power condition.

公开(公告)号：US11011215B1

公开(公告)日：2021-05-18

申请号：US16721373

申请日：2019-12-19

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Michael A. Shore

IPC: G06F13/16 ,  G11C11/406

Abstract: Methods, apparatuses, and systems related to scheduling internal operations are described. An apparatus detects a condition associated with repeated accesses to a memory address and/or region. In response to detection of the condition, the apparatus generates a scheduling output that secures a scheduled duration of inactivity for commanded operations. The apparatus initiates execution of one or more internal operations during the scheduled duration.

公开(公告)号：US11004497B2

公开(公告)日：2021-05-11

申请号：US17018825

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

IPC: G11C7/00 ,  G11C11/406 ,  G11C11/00 ,  G11C11/16 ,  G11C11/22 ,  G11C13/00

Abstract: Provided herein are memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.

公开(公告)号：US20210057279A1

公开(公告)日：2021-02-25

申请号：US16548666

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: H01L21/82 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides, for each respective signal, driving a respective open-drain transistor to conduct, in which an output of each open-drain transistor connects to the common node and the common node connects to a reference voltage, to change a voltage of a common node corresponding to the respective signal; and utilizing the voltage of the common node to indicate total power consumption of the dice.

公开(公告)号：US20210055776A1

公开(公告)日：2021-02-25

申请号：US16548639

申请日：2019-08-22

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  Stephen L. Miller ,  Liang Yu

IPC: G06F1/3225 ,  G06F1/3234 ,  G06F1/3212

Abstract: A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides for converting each respective signal to a respective analog voltage to drive a common node; and utilizing a charge storage device coupled to the common node to accumulate the respective analog voltages from the dice, where the accumulated voltage indicates total power consumption of the dice.

公开(公告)号：US20210011538A1

公开(公告)日：2021-01-14

申请号：US16510696

申请日：2019-07-12

Applicant: Micron Technology, Inc.

Inventor： Jonathan S. Parry ,  David A. Palmer

IPC: G06F1/3225 ,  G06F13/16 ,  G06F1/3234 ,  G06F3/06

Abstract: Exemplary methods, apparatuses, and systems include a first die in a power network receiving, from each of a plurality of dice in the power network, a first activity state value indicating that the respective die is in a high current state, a second activity state value indicating that the respective die is a moderate current state, or a third activity state value indicating that the respective die is a low current state. The received activity state values include at least one second or third activity state value. The first die determines, using the received activity state values, a first sum of the activity state values. The first die further selects an activity state based upon the first sum and sends, to the plurality of dice, an activity state value corresponding to the selected activity state.

公开(公告)号：US10892027B2

公开(公告)日：2021-01-12

申请号：US16543546

申请日：2019-08-17

Applicant: Micron Technology, Inc.

Inventor： Timothy B. Cowles ,  George B. Raad ,  James S. Rehmeyer ,  Jonathan S. Parry

IPC: G11C17/08 ,  G11C17/16 ,  G11C17/18 ,  G11C16/08 ,  G11C16/22 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.