公开(公告)号：US10964592B2

公开(公告)日：2021-03-30

申请号：US16299469

申请日：2019-03-12

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L21/768 ,  H01L21/308 ,  H01L27/108

Abstract: A method of forming conductive vias of integrated circuitry comprises forming first openings in a first masking material, with the first openings being spaced along a line passing across the first openings. Sidewalls of the first openings are lined with a second masking material to form a ring within individual of the first openings and a second opening within the individual first openings radially inside of the ring. The first masking material is removed along the line to form a void space between immediately-adjacent of the rings. A mask is formed that comprises the rings and a third opening in third masking material, with the third opening extending along the line above and across multiple of the rings and multiple of the second openings. The mask is used as an etch mask while etching into substrate material that is exposed through the third opening to form contact openings in the substrate material that are spaced along the line. Conductive material is formed in the contact openings to form conductive vias.

公开(公告)号：US20210013305A1

公开(公告)日：2021-01-14

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US10825484B2

公开(公告)日：2020-11-03

申请号：US16702926

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Si-Woo Lee

IPC: G11C5/10 ,  H01L27/108 ,  G11C11/401

Abstract: A method of forming an integrated assembly includes providing a construction having laterally-spaced digit-line-contact-regions and having intervening regions between the laterally-spaced digit-line-contact-regions; forming an expanse of non-conductive-semiconductor-material which extends across the digit-line-contact-regions and the intervening regions; a lower surface of the non-conductive-semiconductor-material being vertically-spaced from upper surfaces of the digit-line-contact-regions; forming openings extending through the non-conductive-semiconductor-material to the digit-line-contact-regions; forming conductive-semiconductor-material-interconnects within the openings and coupled with the digit-line-contact-regions, upper surfaces of the conductive-semiconductor-material-interconnects being beneath the lower surface of the non-conductive-semiconductor-material; and forming metal-containing-digit-lines over the non-conductive-semiconductor-material.

公开(公告)号：US10734388B1

公开(公告)日：2020-08-04

申请号：US16248534

申请日：2019-01-15

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US10566334B2

公开(公告)日：2020-02-18

申请号：US15977622

申请日：2018-05-11

Applicant: Micron Technology, Inc.

Inventor： Si-Woo Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/522

Abstract: Integrated circuitry comprises a first conductive line buried within semiconductive material of a substrate. The first conductive line comprises conductively-doped semiconductor material directly above and directly against metal material in a vertical cross-section. A second conductive line is above the semiconductive material and is laterally-spaced from the first conductive line in the vertical cross-section. The second conductive line comprises metal material in the vertical cross-section. Insulative material is directly above the first and second conductive lines. A first conductive via extends through the insulative material and through the conductively-doped semiconductor material to the metal material of the first conductive line. A second conductive via extends through the insulative material to the metal material of the second conductive line. Other embodiments and aspects, including method, are disclosed.

公开(公告)号：US20190287605A1

公开(公告)日：2019-09-19

申请号：US16431500

申请日：2019-06-04

Applicant: Micron Technology, Inc.

Inventor： Tae H. Kim ,  Sangmin Hwang ,  Si-Woo Lee

IPC: G11C11/4091 ,  G11C11/22 ,  G11C11/4097

Abstract: Some embodiments include an apparatus having first and second comparative bitlines extending horizontally and coupled with a sense amplifier. First memory cell structures are coupled with the first comparative bitline. Each of the first memory cell structures has a first transistor associated with a first capacitor. Second memory cell structures are coupled with the second comparative bitline. Each of the second memory cell structures has a second transistor associated with a second capacitor. Each of the first capacitors has a container-shaped first node and is vertically offset from an associated first sister capacitor which is a mirror image of its associated first capacitor along a horizontal plane. Each of the second capacitors has a container-shaped first node and is vertically offset from an associated second sister capacitor which is a mirror image of its associated second capacitor along the horizontal plane.

公开(公告)号：US20160104709A1

公开(公告)日：2016-04-14

申请号：US14511371

申请日：2014-10-10

Applicant: Micron Technology, Inc.

Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

IPC: H01L27/108 ,  G11C11/407

CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。