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    Apparatuses and systems for providing power to a memory
    1.
    发明授权
    Apparatuses and systems for providing power to a memory 有权

    公开(公告)号：US11621031B2

    公开(公告)日：2023-04-04

    申请号：US17302206

    申请日：2021-04-27

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Hyun Yoo Lee ,  Kang-Yong Kim ,  Sourabh Dhir ,  Keun Soo Song

    IPC: G11C5/14 ,  G11C11/4074

    Abstract: In some examples, memory die may include a selection pad, which may be coupled to a power potential. The selection pad may provide a signal to a selection control circuit, which may control a selection circuit to couple a power pad to one of multiple power rails. In some examples, a power management integrated circuit may include a selection circuit to provide one power potential to a package including a memory die when a selection signal has a logic level and another power potential when the selection signal has another logic level.

    INTER-MEMORY MOVEMENT IN A MULTI-MEMORY SYSTEM
    2.
    发明申请
    INTER-MEMORY MOVEMENT IN A MULTI-MEMORY SYSTEM 有权

    公开(公告)号：US20220066675A1

    公开(公告)日：2022-03-03

    申请号：US17018570

    申请日：2020-09-11

    Applicant: Micron Technology, Inc.

    Inventor： Sourabh Dhir ,  Kang-Yong Kim

    IPC: G06F3/06

    Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

    Inter-memory movement in a multi-memory system
    3.
    发明授权
    Inter-memory movement in a multi-memory system 有权

    公开(公告)号：US12164795B2

    公开(公告)日：2024-12-10

    申请号：US18390844

    申请日：2023-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Sourabh Dhir ,  Kang-Yong Kim

    IPC: G06F12/00 ,  G06F3/06

    Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING VERTICAL MEMORY CELLS AND METHODS OF FORMING SAME 有权
    包括垂直存储器单元的半导体器件及其形成方法

    公开(公告)号：US20150129955A1

    公开(公告)日：2015-05-14

    申请号：US14075480

    申请日：2013-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Wolfgang Mueller ,  Sanh D. Tang ,  Sourabh Dhir ,  Srinivas Pulugurtha

    IPC: H01L29/78 ,  H01L27/105 ,  H01L29/66

    CPC classification number: H01L29/7827 ,  G11C11/40 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/10855 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/10891 ,  H01L29/66666

    Abstract: A semiconductor device may include a memory array including vertical memory cells connected to a digit line, word lines, and a body connection line. A row or column of the memory array may include one or more pillars connected to the body connection line. A voltage may be applied to the body connection line through at least one pillar connected to the body connection line. Application of the voltage to the body connection line may reduce floating body effects. Methods of forming a connection between at least one pillar and a voltage supply are disclosed. Semiconductor devices including such connections are also disclosed.

    Abstract translation: 半导体器件可以包括存储器阵列，其包括连接到数字线，字线和主体连接线的垂直存储器单元。 存储器阵列的行或列可以包括连接到主体连接线的一个或多个支柱。 可以通过连接到主体连接线的至少一个支柱将电压施加到主体连接线。 施加电压到身体连接线可能会减少浮体效应。 公开了形成至少一个柱和电压源之间的连接的方法。 还公开了包括这种连接的半导体器件。

    Vapor-etch cyclic process
    7.
    发明授权
    Vapor-etch cyclic process 有权

    公开(公告)号：US10607851B2

    公开(公告)日：2020-03-31

    申请号：US15686526

    申请日：2017-08-25

    Applicant: Micron Technology, Inc.

    Inventor： Andrew L. Li ,  Prashant Raghu ,  Sanjeev Sapra ,  Rita J. Klein ,  Sanh D. Tang ,  Sourabh Dhir

    IPC: H01L21/00 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L21/66 ,  H01L21/67 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66

    Abstract: Various embodiments comprise methods of selectively etching oxides over nitrides in a vapor-etch cyclic process. In one embodiment, the method includes, in a first portion of the vapor-etch cyclic process, exposing a substrate having oxide features and nitride features formed thereon to selected etchants in a vapor-phase chamber; transferring the substrate to a post-etch heat treatment chamber; and heating the substrate to remove etchant reaction products from the substrate. In a second portion of the vapor-etch cyclic process, the method continues with transferring the substrate from the post-etch heat treatment chamber to the vapor-phase chamber; exposing the substrate to the selected etchants in the vapor-phase chamber; transferring the substrate to the post-etch heat treatment chamber; and heating the substrate to remove additional etchant reaction products from the substrate. Apparatuses for performing the method and additional methods are also disclosed.

    Passing access line structure in a memory device
    10.
    发明授权
    Passing access line structure in a memory device 有权
    在存储设备中传递访问线路结构

    公开(公告)号：US09349737B2

    公开(公告)日：2016-05-24

    申请号：US14511371

    申请日：2014-10-10

    Applicant: Micron Technology, Inc.

    Inventor： Srinivas Pulugurtha ,  Sourabh Dhir ,  Rajesh N. Gupta ,  Sanh D. Tang ,  Si-Woo Lee ,  Haitao Liu

    IPC: H01L27/105 ,  H01L27/108 ,  G11C11/407

    CPC classification number: H01L27/10826 ,  G11C7/02 ,  G11C11/407 ,  G11C11/4097 ,  H01L27/10879

    Abstract: A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The continuous fins are etched into segmented fins to form exposed areas between the segmented fins. An insulator material is formed in the exposed areas wherein the insulator material in the exposed areas is formed higher than the insulator material around the fins. A metal is formed over the fins and the insulator material. The metal formed over the exposed areas is formed to a shallower depth than over the fins.

    Abstract translation: 用于存储器件制造的方法包括在衬底上形成多个连续的翅片。 在翅片周围形成绝缘体材料。 将连续的翅片蚀刻成分段的翅片以在分段翅片之间形成暴露的区域。 在暴露区域中形成绝缘体材料，其中暴露区域中的绝缘体材料形成为高于鳍片周围的绝缘体材料。 在翅片和绝缘体材料上形成金属。 形成在暴露区域上的金属形成为比鳍片上方浅的深度。

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