公开(公告)号：US20220261253A1

公开(公告)日：2022-08-18

申请号：US17737922

申请日：2022-05-05

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06F9/345 ,  G06F9/355

Abstract: Disclosed herein are vector index registers in vector processors that each store multiple addresses for accessing multiple positions in vectors. It is known to use scalar index registers in vector processors to access multiple positions of vectors by changing the scalar index registers in vector operations. By using a vector indexing register for indexing positions of one or more operand vectors, the scalar index register can be replaced and at least the continual changing of the scalar index register can be avoided.

公开(公告)号：US11372648B2

公开(公告)日：2022-06-28

申请号：US17158999

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F13/16 ,  G06F12/0842

Abstract: A cache system having cache sets, registers associated with the cache sets respectively, and a logic circuit coupled to a processor to control the cache sets according to the registers. When a connection to an address bus of the system receives a memory address from the processor, the logic circuit can be configured to: generate an extended tag from at least the memory address; and determine whether the generated extended tag matches with a first extended tag for a first cache set or a second extended tag for a second cache set of the system. Also, the logic circuit can also be configured to implement a command received from the processor via the first cache set in response to the generated extended tag matching with the first extended tag and via the second cache set in response to the generated extended tag matching with the second extended tag.

公开(公告)号：US11237970B2

公开(公告)日：2022-02-01

申请号：US16183661

申请日：2018-11-07

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/0842

Abstract: A computing system, method and apparatus to cache a portion of a data block. A processor can access data using memory addresses in an address space. A first memory can store a block of data at a block of contiguous addresses in the space of memory address. A second memory can cache a first portion of the block of data identified by an item selection vector. For example, response to a request to cache the block of data stored in the first memory, the computing system can communicate the first portion of the block of data from the first memory to the second memory according to the item selection vector without accessing a second portion of the block of data. Thus, different data blocks in the first memory of a same size can be each cached in different cache blocks of different sizes in the second memory.

公开(公告)号：US20210326264A1

公开(公告)日：2021-10-21

申请号：US17358861

申请日：2021-06-25

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/0864 ,  G06F13/16 ,  G06F9/30 ,  G06F9/38

Abstract: A cache system, having: a first cache set; a second cache set; and a logic circuit coupled to a processor to control the caches based on at least respective first and second registers. When a connection to an address bus receives a memory address from the processor, the logic circuit is configured to: generate a set index from at least the address; and determine whether the generated set index matches with a content stored in the first register or with a content stored in the second register. And, the logic circuit is configured to implement a command via the first cache set in response to the generated set index matching with the content stored in the first register and via the second cache set in response to the generated set index matching with the content stored in the second register.

公开(公告)号：US11113422B2

公开(公告)日：2021-09-07

申请号：US16054913

申请日：2018-08-03

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/71 ,  G06F9/30 ,  G06F21/60 ,  G06F12/14 ,  G06F12/0802

Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a cache, a register, an execution unit, and an unscrambler. The processor can load the scrambled data into the cache; and the unscrambler may convert the scrambled data into unscrambled data just in time for the register or the execution unit during instruction execution. The unscrambled data can be an instruction, an address, or an operand of an instruction. Unscrambling can be performed just before loading the data item in a scrambled form from the cache into the register in an unscrambled form, or after the data item leaves the register in the scrambled form as input to the execution unit in the unscrambled form. The unscrambled data and the scrambled data may have the same set of bits arranged in different orders.

公开(公告)号：US11074198B2

公开(公告)日：2021-07-27

申请号：US16134387

申请日：2018-09-18

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F21/00 ,  G06F12/14 ,  G06F12/1018 ,  G06F21/79 ,  G06F21/60 ,  H04L9/08 ,  G06F21/71

Abstract: Systems, apparatuses, and methods related to a computer system having a processor and a main memory storing scrambled data are described. The processor may have a secure zone configured to store keys and an unscrambled zone configured to operate on unscrambled data. The processor can convert the scrambled data into the unscrambled data in the unscrambled zone using the keys retrieved from the secure zone in response to execution of instructions configured to operate on the unscrambled data. Another processor may also be coupled with the memory, but can be prevented from accessing the unscrambled data in the unscrambled zone.

公开(公告)号：US20210208892A1

公开(公告)日：2021-07-08

申请号：US17189151

申请日：2021-03-01

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F12/0875 ,  G06F12/0891

Abstract: A computing device, having: a processor; memory; a first cache coupled between the memory and the processor; and a second cache coupled between the memory and the processor. During speculative execution of one or more instructions, effects of the speculative execution are contained within the second cache.

公开(公告)号：US20210157599A1

公开(公告)日：2021-05-27

申请号：US17163163

申请日：2021-01-29

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0842 ,  G06F13/16

Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.

公开(公告)号：US20210149817A1

公开(公告)日：2021-05-20

申请号：US17158979

申请日：2021-01-26

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F12/1009 ,  G06F9/455 ,  G06F12/14 ,  G11C11/16 ,  G11C8/20

Abstract: Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

公开(公告)号：US10915326B1

公开(公告)日：2021-02-09

申请号：US16528479

申请日：2019-07-31

Applicant: Micron Technology, Inc.

Inventor： Steven Jeffrey Wallach

IPC: G06F9/38 ,  G06F9/30 ,  G06F12/0842 ,  G06F13/16

Abstract: A cache system, having a first cache, a second cache, and a logic circuit coupled to control the first cache and the second cache according to an execution type of a processor. When an execution type of a processor is a first type indicating non-speculative execution of instructions and the first cache is configured to service commands from a command bus for accessing a memory system, the logic circuit is configured to copy a portion of content cached in the first cache to the second cache. The cache system can include a configurable data bit. The logic circuit can be coupled to control the caches according to the bit. Alternatively, the caches can include cache sets. The caches can also include registers associated with the cache sets respectively. The logic circuit can be coupled to control the cache sets according to the registers.