LAMINATED CERAMIC ELECTRONIC COMPONENT AND METHOD OF FABRICATING THE SAME
    102.
    发明申请
    LAMINATED CERAMIC ELECTRONIC COMPONENT AND METHOD OF FABRICATING THE SAME 有权
    层压陶瓷电子元件及其制造方法

    公开(公告)号:US20140022692A1

    公开(公告)日:2014-01-23

    申请号:US13839781

    申请日:2013-03-15

    CPC classification number: H01G4/12 H01G4/1227 H01G4/30

    Abstract: There are provided a laminated ceramic electronic component and a method of fabricating the same. The laminated ceramic electronic component include a ceramic body including a dielectric layer; and first and second internal electrodes disposed to face each other, having the dielectric layer interposed therebetween within the ceramic body, wherein the ceramic body includes an active layer that is a capacitance forming part and a cover layer that is a non-capacitance forming part formed on at least one of a top surface and a bottom surface of the active layer, and when a thickness of the ceramic body is t and a thickness of the cover layer is T, T≦t×0.05 is satisfied and when an average particle diameter of a dielectric grain in the active layer is Da and an average particle diameter of a dielectric grain in the cover layer is Dc, 0.7≦Dc/Da≦1.5 is satisfied.

    Abstract translation: 提供层叠陶瓷电子部件及其制造方法。 层叠陶瓷电子部件包括:陶瓷体,其包括电介质层; 以及第一和第二内部电极,所述第一和第二内部电极彼此相对设置,所述陶瓷体在陶瓷体内具有介电层,其中所述陶瓷体包括作为电容形成部的有源层和形成为非电容形成部的覆盖层 在活性层的上表面和底面中的至少一个上,当陶瓷体的厚度为t,覆盖层的厚度为T时,满足T@t×0.05,当平均粒径 在有源层中的电介质晶粒为Da,覆盖层中的电介质晶粒的平均粒径为Dc,满足0.7 @ Dc / Da @ 1.5。

    ARRAY-TYPE MULTILAYERED CERAMIC ELECTRONIC COMPONENT
    103.
    发明申请
    ARRAY-TYPE MULTILAYERED CERAMIC ELECTRONIC COMPONENT 有权
    阵列型多层陶瓷电子元件

    公开(公告)号:US20130201603A1

    公开(公告)日:2013-08-08

    申请号:US13678106

    申请日:2012-11-15

    CPC classification number: H01G4/012 H01G4/232 H01G4/30

    Abstract: There is provided an array-type multilayered ceramic electronic component including: a ceramic body; a plurality of external electrodes formed on one surface of the ceramic body and the other surface thereof opposing the one surface; and a plurality of internal electrode multilayered parts formed in the ceramic body and connected to the external electrodes, respectively, wherein when a gap between the internal electrode multilayered parts is G and internal electrode density is D, 40%≦D≦57%, 10 μm≦G≦200 μm, and G≧(0.0577×D2)−(4.4668×D)+111.22. Therefore, delamination and cracking may be prevented.

    Abstract translation: 提供了一种阵列型多层陶瓷电子部件,包括:陶瓷体; 形成在所述陶瓷体的一个表面上的多个外部电极和与所述一个表面相对的另一个表面; 以及分别形成在陶瓷体中并与外部电极连接的多个内部电极多层部分,其中当内部电极多层部分之间的间隙为G且内部电极密度为D时,40%@ D @ 57%,10 m @ @ @ 200mum,G> =(0.0577×D2) - (4.4668×D)+111.22。 因此,可以防止分层和破裂。

    MULTILAYER CERAMIC ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME
    104.
    发明申请
    MULTILAYER CERAMIC ELECTRONIC PART AND METHOD OF MANUFACTURING THE SAME 审中-公开
    多层陶瓷电子部件及其制造方法

    公开(公告)号:US20130120900A1

    公开(公告)日:2013-05-16

    申请号:US13670074

    申请日:2012-11-06

    CPC classification number: H01G4/005 H01G4/012 H01G4/12 H01G4/232 H01G4/30

    Abstract: There is provided a multilayer ceramic electronic part, including: a ceramic element having a plurality of dielectric layers laminated therein; first and second internal electrodes formed on at least one surface of each of the plurality of dielectric layers within the ceramic element and exposed through one surface of the ceramic element; and first and second external electrodes formed on one surface of the ceramic element and electrically connected to the first and second internal electrodes through exposed portions of the respective first and second internal electrodes, wherein a ratio of an area of the first or second external electrode to an area of one surface of the ceramic element is 10 to 40%.

    Abstract translation: 提供了一种多层陶瓷电子部件,其包括:陶瓷元件,其中层叠有多个电介质层; 第一和第二内部电极,其形成在所述陶瓷元件内的所述多个介电层中的每一个的至少一个表面上,并且通过所述陶瓷元件的一个表面暴露; 以及第一外部电极和第二外部电极,其形成在陶瓷元件的一个表面上,并通过各个第一和第二内部电极的暴露部分与第一和第二内部电极电连接,其中第一或第二外部电极的面积与 陶瓷元件的一个面的面积为10〜40%。

    CHIP TYPE LAMINATED CAPACITOR
    105.
    发明申请
    CHIP TYPE LAMINATED CAPACITOR 有权
    芯片型层压电容器

    公开(公告)号:US20130094123A1

    公开(公告)日:2013-04-18

    申请号:US13693947

    申请日:2012-12-04

    Abstract: There is provided a chip type laminated capacitor including: a ceramic body formed by laminating a dielectric layer having a thickness equal to 10 or more times an average particle diameter of a grain included therein and being 3 μm or less; first and second outer electrodes; a first inner electrode having one end forming a first margin together with one end surface of the ceramic body at which the second outer electrode is formed and the other end leading to the first outer electrode; and a second inner electrode having one end forming a second margin together with the other end surface of the ceramic body at which the first outer electrode is formed and the other end leading to the second outer electrode, wherein the first and second margins have different widths under a condition that they are 200 μm or less.

    Abstract translation: 提供一种片式叠层电容器,其包括:陶瓷体,其通过层叠厚度等于其中包含的颗粒的平均粒径的10倍或更多倍的3μm或更小的电介质层而形成; 第一和第二外部电极; 第一内部电极,其一端与形成有第二外部电极的陶瓷体的一个端面一起形成第一边缘,而另一端通向第一外部电极; 以及第二内部电极,其一端与形成有第一外部电极的陶瓷体的另一个端面一起形成第二边缘,另一端通向第二外部电极,其中第一和第二边缘具有不同的宽度 条件是他们是200毫米或更少。

Patent Agency Ranking