公开(公告)号：US20220356562A1

公开(公告)日：2022-11-10

申请号：US17869174

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Yi-Ming Dai

IPC: C23C16/02 ,  C23C16/458 ,  C23C14/34 ,  C23C14/02 ,  C23C16/46 ,  C23C16/34

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

公开(公告)号：US11462394B2

公开(公告)日：2022-10-04

申请号：US16572186

申请日：2019-09-16

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chia-Hsi Wang ,  Kun-Che Ho ,  Yen-Yu Chen

IPC: H01J37/34 ,  C23C14/34 ,  C23C14/35 ,  H01L21/02

Abstract: A PVD method includes tilting a first magnetic element over a back side of a target. The first magnetic element is moved about an axis that extends through the target. Then, charged ions are attracted to bombard the target, such that particles are ejected from the target and are deposited over a surface of a wafer. By tilting the magnetic element relative to the target, the distribution of the magnetic fields can be more random and uniform.

公开(公告)号：US20220293770A1

公开(公告)日：2022-09-15

申请号：US17827542

申请日：2022-05-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L21/285 ,  H01L21/768

Abstract: A semiconductor device includes a first cobalt-containing plug disposed over a substrate, a second cobalt-containing plug disposed over the first cobalt-containing plug, a first barrier layer over sidewalls of the second cobalt-containing plug, a second barrier layer over sidewalls of the first barrier layer, and a dielectric layer surrounding the second barrier layer. The first barrier layer contains a metal element. The first and second barrier layers include different material compositions.

公开(公告)号：US20220254687A1

公开(公告)日：2022-08-11

申请号：US17734327

申请日：2022-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Wei-Jen Chen ,  Yen-Yu Chen ,  Ming-Hsien Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/088

Abstract: Methods for tuning threshold voltages of fin-like field effect transistor (FinFET) devices are disclosed herein. An exemplary integrated circuit device includes a high voltage n-type FinFET, a high voltage p-type FinFET, a low voltage n-type FinFET, and a low voltage p-type FinFET. Threshold voltages of the high voltage n-type FinFET and the high voltage p-type FinFET are greater than threshold voltages of the low voltage n-type FinFET and the low voltage p-type FinFET, respectively. The high voltage n-type FinFET, the high voltage p-type FinFET, the low voltage n-type FinFET, and the low voltage p-type FinFET each include a threshold voltage tuning layer that includes tantalum and nitrogen. Thicknesses of the threshold voltage tuning layer of the low voltage n-type FinFET and the low voltage p-type FinFET are less than thicknesses of the threshold voltage tuning layer of the high voltage n-type FinFET and the high voltage p-type FinFET, respectively.

公开(公告)号：US20220173036A1

公开(公告)日：2022-06-02

申请号：US17675302

申请日：2022-02-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L23/532

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

公开(公告)号：US11349015B2

公开(公告)日：2022-05-31

申请号：US16870360

申请日：2020-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Yen-Yu Chen

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L21/762 ,  H01L21/285 ,  H01L21/768

Abstract: A semiconductor device includes a conductive feature over a substrate, a ruthenium-containing feature disposed over the conductive feature, and a first barrier layer disposed over the conductive feature and over sidewalls of the ruthenium-containing feature. The semiconductor device also includes a second barrier layer disposed over sidewalls of the first barrier layer, and a third barrier layer disposed over sidewalls of the second barrier layer. The first, second, and third barrier layers include different material compositions.

公开(公告)号：US11257755B2

公开(公告)日：2022-02-22

申请号：US16901688

申请日：2020-06-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Yu Chen ,  Chung-Liang Cheng

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/535 ,  H01L21/02 ,  H01L23/532

Abstract: The present disclosure describes a method for forming a barrier structure between liner-free conductive structures and underlying conductive structures. The method includes forming openings in a dielectric layer disposed on a contact layer, where the openings expose conductive structures in the contact layer. A first metal layer is deposited in the openings and is grown thicker on top surfaces of the conductive structures and thinner on sidewall surfaces of the openings. The method further includes exposing the first metal layer to ammonia to form a bilayer with the first metal layer and a nitride of the first metal layer, and subsequently exposing the nitride to an oxygen plasma to convert a portion of the nitride of the first metal layer to an oxide layer. The method also includes removing the oxide layer and forming a semiconductor-containing layer on the nitride of the first metal layer.

公开(公告)号：US20210391251A1

公开(公告)日：2021-12-16

申请号：US16900567

申请日：2020-06-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung Hsun Lin ,  Che-Chih Hsu ,  Wen-Chu Huang ,  Chinyu Su ,  Yen-Yu Chen ,  Wei-Chun Hua ,  Wen Han Hung

IPC: H01L23/522 ,  H01L23/66 ,  H01L23/64 ,  H01L21/768 ,  H01L49/02

Abstract: A device includes a substrate, a first conductive layer on the substrate, a first conductive via, and further conductive layers and conductive vias between the first conductive via and the substrate. The first conductive via is between the substrate and the first conductive layer, and is electrically connected to the first conductive layer. The first conductive via extends through at least two dielectric layers, and has thickness greater than about 8 kilo-Angstroms. An inductor having high quality factor is formed in the first conductive layer and also includes the first conductive via.

公开(公告)号：US11201059B2

公开(公告)日：2021-12-14

申请号：US16701009

申请日：2019-12-02

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu Chen ,  Yu-Chi Lu ,  Chih-Pin Tsao ,  Shih-Hsun Chang

IPC: H01L21/28 ,  H01L29/49

Abstract: A method includes removing a dummy gate to form a gate trench. A gate dielectric layer is deposited over a bottom and sidewalls of the gate trench. A first work function metal layer is deposited over the gate dielectric layer. A dummy layer is deposited over the first work function metal layer. An impurity is introduced into the dummy layer and the first work function metal layer after the dummy layer is deposited. The dummy layer is removed after the impurity is introduced into the dummy layer and the first work function metal layer. The gate trench is filled with a conductive material after the dummy layer is removed.

公开(公告)号：US11075179B2

公开(公告)日：2021-07-27

申请号：US16430075

申请日：2019-06-03

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Wen-Hao Cheng ,  Yen-Yu Chen ,  Chih-Wei Lin ,  Yi-Ming Dai

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/522

Abstract: A method for forming a bond pad structure includes forming an interconnect structure on a semiconductor device, forming a passivation layer on the interconnect structure, forming at least one opening through the passivation layer, forming an oxidation layer at least in the opening, and forming a pad metal layer on the oxidation layer. A portion of the interconnect structure is exposed by the at least one opening.