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    Fluorine contamination control in semiconductor manufacturing process
    3.
    发明授权
    Fluorine contamination control in semiconductor manufacturing process 有权

    公开(公告)号：US10262878B2

    公开(公告)日：2019-04-16

    申请号：US16155186

    申请日：2018-10-09

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Li-Jung Liu ,  Chih-Pin Tsao ,  Chia-Wei Soong ,  Jyh-Huei Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

    IPC分类号： H01L27/088 ,  H01L21/67 ,  H01L29/78 ,  H01L23/485 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/027 ,  H01J37/32

    摘要： A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

    Fluorine contamination control in semiconductor manufacturing process
    4.
    发明授权
    Fluorine contamination control in semiconductor manufacturing process 有权

    公开(公告)号：US10109507B2

    公开(公告)日：2018-10-23

    申请号：US15609199

    申请日：2017-05-31

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Li-Jung Liu ,  Chih-Pin Tsao ,  Chia-Wei Soong ,  Jyh-Huei Chen ,  Shu-Hui Wang ,  Shih-Hsun Chang

    IPC分类号： H01L21/84 ,  H01L21/67 ,  H01L21/311 ,  H01L21/027 ,  H01J37/32 ,  H01L21/3065

    摘要： A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the polysilicon gate structure with a metal gate structure. Replacing of the polysilicon gate structure includes depositing a work function metal layer over the fin, performing a sublimation process on a non-fluorine based metal precursor to produce a gaseous non-fluorine based metal precursor, and depositing a substantially fluorine-free metal layer over the work function metal layer based on the gaseous non-fluorine based metal precursor. The substantially fluorine-free metal layer includes an amount of fluorine less than about 5 atomic percent. An example benefit includes reduction or elimination of diffusion of fluorine contaminants from a gate metal fill layer into its underlying layers and from conductive layers into diffusion barrier layers and silicide layers of source/drain contact structures and consequently, the reduction of the negative impact of these fluorine contaminants on device performance.

    FinFET and gate-all-around FET with selective high-k oxide deposition
    6.
    发明授权
    FinFET and gate-all-around FET with selective high-k oxide deposition 有权

    公开(公告)号：US11177361B2

    公开(公告)日：2021-11-16

    申请号：US16889245

    申请日：2020-06-01

    申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

    发明人： Tsung-Han Tsai ,  Jen-Hsiang Lu ,  Shih-Hsun Chang

    IPC分类号： H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/40 ,  H01L21/02 ,  H01L29/78

    摘要： A semiconductor device structure is provided. The semiconductor device structure includes a fin structure formed over a semiconductor substrate and a gate structure formed across the fin structure. The semiconductor device structure also includes an isolation feature over a semiconductor substrate and below a portion of the gate structure and two spacer elements respectively formed over a first sidewall and a second sidewall of the gate structure. In addition, the first sidewall is opposite to the second sidewall and the two spacer elements have hydrophobic surfaces respectively facing the first sidewall and the second sidewall, and the gate structure includes a gate dielectric layer and a gate electrode layer separating the gate dielectric layer from the hydrophobic surfaces of the two spacer elements.