公开(公告)号：US10991757B2

公开(公告)日：2021-04-27

申请号：US16430437

申请日：2019-06-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ting-Hsiang Huang ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chih-Kai Kang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor device includes: a substrate having a magnetic tunneling junction (MTJ) region and a logic region; a magnetic tunneling junction (MTJ) on the MTJ region, wherein a top view of the MTJ comprises a circle; and a first metal interconnection on the MTJ. Preferably, a top view of the first metal interconnection comprises a flat oval overlapping the circle.

公开(公告)号：US10983428B2

公开(公告)日：2021-04-20

申请号：US15978215

申请日：2018-05-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh

IPC: G06F30/39 ,  G03F1/36

Abstract: A mask includes a substrate, a main pattern, a first assist pattern, and a second assist pattern. The main pattern is disposed on the substrate. The main pattern includes a first pattern and second patterns. Two of the second patterns are disposed at two opposite sides of the first pattern in a first direction. The first assist pattern is disposed on the substrate and disposed in the main pattern. The second assist pattern is disposed on the substrate and disposed outside the main pattern. The first assist pattern disposed in the main pattern may be used to improve the pattern transferring performance in a photolithography process using the mask.

公开(公告)号：US20210082911A1

公开(公告)日：2021-03-18

申请号：US16596764

申请日：2019-10-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yung-Chen Chiu ,  Sheng-Yuan Hsueh ,  Kuo-Hsing Lee ,  Chien-Liang Wu ,  Chih-Kai Kang ,  Guan-Kai Huang

IPC: H01L27/06 ,  H01L29/778 ,  H01L29/66 ,  H01L27/085

Abstract: A 3D semiconductor structure includes a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface.

公开(公告)号：US20190067204A1

公开(公告)日：2019-02-28

申请号：US15715184

申请日：2017-09-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Chen Sun ,  Yu-Cheng Tung ,  Sheng-Yuan Hsueh ,  Fan-Wei Lin

IPC: H01L23/544 ,  H01L21/66 ,  G01B21/24

Abstract: The present invention provides an alignment mark, the alignment mark includes at least one dummy mark pattern in a first layer comprises a plurality of dummy mark units arranged along a first direction, and at least one first mark pattern located in a second layer disposed above the first layer, the first mark pattern comprises a plurality of first mark units, each of the first mark units being arranged in a first direction. When viewed in a top view, the first mark pattern completely covers the dummy mark pattern, and the size of each dummy mark unit is smaller than each first mark unit. In addition, each dummy mark unit of the dummy mark pattern has a first width, each first mark unit of the first mark pattern has a second width, and the first width is smaller than half of the second width.

公开(公告)号：US20180151555A1

公开(公告)日：2018-05-31

申请号：US15365906

申请日：2016-11-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Hsien Chen ,  Sheng-Yuan Hsueh ,  Yi-Chung Sheng ,  Chih-Kai Kang ,  Wen-Kai Lin ,  Shu-Hung Yu

IPC: H01L27/06 ,  H01L49/02 ,  H01L29/06 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L27/0629 ,  H01L21/76897 ,  H01L23/5283 ,  H01L28/60 ,  H01L29/0649

Abstract: An intra-metal capacitor is provided. The intra-metal capacitor is formed in a dielectric layer and comprising a first electrode and a second electrode, wherein the first electrode penetrate through the whole thickness of the dielectric layer, and the second electrode does not penetrate through the whole thickness of the dielectric layer.