公开(公告)号：US5315069A

公开(公告)日：1994-05-24

申请号：US955928

申请日：1992-10-02

Applicant: Ghassan R. Gebara

Inventor： Ghassan R. Gebara

IPC: H05K1/02 ,  H05K9/00 ,  H05K1/00

CPC classification number: H05K1/0218 ,  H05K9/0039 ,  H05K1/0219 ,  H05K2201/093

Abstract: An EMR reduction technique using grounded conductive traces and vias circumscribing the internal planes of printed wiring boards. Conductive vias are placed in a circuitous path near the border and encircling the signal traces of each layer of a printed circuit board. The ground plane is extended to encompass and electrically ground each of the vias. For each signal plane, a conductive trace is routed and connected to each of the vias forming a grounded shield around the signal-carrying traces on the signal plane. For the power planes, a conductive trace is also provided connecting the conductive vias and forming a grounded shield around the power planes. A non-conductive path is provided between the power plane and the power plane conductive trace to electrically isolate the voltages of the power plane from the grounded conductive trace.

Abstract translation: 使用接地导电迹线和通孔限制印刷电路板的内部平面的EMR降低技术。 导电通孔放置在靠近边界的迂回路径中并且环绕印刷电路板的各层的信号迹线。 接地平面被延伸以包围和电接地每个通孔。 对于每个信号平面，导电迹线被路由并连接到在信号平面上的信号载体迹线周围形成接地屏蔽的每个通孔。 对于电源平面，还提供连接导电通孔并在电源平面周围形成接地屏蔽的导电迹线。 在电源平面和电源平面导电迹线之间提供非导电路径，以将电源平面的电压与接地的导电迹线电隔离。

公开(公告)号：US5305013A

公开(公告)日：1994-04-19

申请号：US612134

申请日：1990-11-13

Applicant: George R. Daniels

Inventor： George R. Daniels

IPC: G06F1/18 ,  G06F11/32 ,  G09F9/33 ,  G09F13/22 ,  G11B33/10 ,  G09G3/32

CPC classification number: G11B33/10 ,  G06F1/181 ,  G06F11/326 ,  G09F13/22 ,  G09F9/33 ,  G06F11/324 ,  G09F2013/222 ,  Y10S345/904

Abstract: A graphical display icon on the front of a data storage unit provides status information on disk drives within the unit. The icon has a shape identical to that of the unit and includes a number of bicolor LED's which each correspond to a similarly situated disk drive located in the unit. The color emitted by the LED's communicate information on the status of the corresponding disk drive within the unit.

Abstract translation: 数据存储单元正面的图形显示图标提供了本机内磁盘驱动器的状态信息。 该图标具有与该单元相同的形状，并且包括多个双色LED，每个双色LED对应于位于该单元中的类似位置的磁盘驱动器。 LED发出的颜色与单元内相应磁盘驱动器的状态信息进行通信。

公开(公告)号：US5287531A

公开(公告)日：1994-02-15

申请号：US606165

申请日：1990-10-31

Applicant: Harry R. Rogers, Jr. ,  John A. Landry ,  Javier F. Izquierdo

Inventor： Harry R. Rogers, Jr. ,  John A. Landry ,  Javier F. Izquierdo

IPC: G06F12/06 ,  G06F12/02

CPC classification number: G06F12/0684

Abstract: An apparatus for determining system configuration in a computer system using only one 8 bit data port. Permanent connections on each of the microprocessor and memory boards provide respective configuration and/or memory information about each board. The signals are stored in serial out shift registers associated with each board that are daisy chained together. These shift registers serially transmit the configuration information to one 8 bit data port, which then transmits this information to the computer system in 8 bit increments. If a given slot is empty it is automatically bypassed in the shift register daisy chain.

Abstract translation: 一种用于在仅使用一个8位数据端口的计算机系统中确定系统配置的装置。 每个微处理器和存储器板上的永久连接提供关于每个板的相应配置和/或存储器信息。 这些信号存储在串联输出移位寄存器中，每个板与菊花链连接在一起。 这些移位寄存器将配置信息串行发送到一个8位数据端口，然后以8位增量将该信息发送到计算机系统。 如果给定的时隙为空，则会在移位寄存器菊花链中自动旁路。

公开(公告)号：US2482493A

公开(公告)日：1949-09-20

申请号：US62015145

申请日：1945-10-03

Applicant: RCA CORP

Inventor： KING LOUIS A

IPC: H05B6/04

CPC classification number: H05B6/04

公开(公告)号：US2017130A

公开(公告)日：1935-10-15

申请号：US71911934

申请日：1934-04-05

Applicant: BELL TELEPHONE LABOR INC

Inventor： PERREAULT GEORGE E

IPC: H04N5/66

CPC classification number: H04N5/66

公开(公告)号：US6085263A

公开(公告)日：2000-07-04

申请号：US956861

申请日：1997-10-24

Applicant: Madhumitra Sharma ,  Chester Pawlowski ,  Kourosh Gharachorloo ,  Stephen R. Van Doren ,  Simon C. Steely, Jr.

Inventor： Madhumitra Sharma ,  Chester Pawlowski ,  Kourosh Gharachorloo ,  Stephen R. Van Doren ,  Simon C. Steely, Jr.

IPC: G06F12/08 ,  G06F13/12 ,  G06F13/14

CPC classification number: G06F12/082 ,  G06F13/124 ,  G06F12/0862 ,  G06F2212/621

Abstract: An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP comprises a retire controller which imposes inter-reference ordering among the operations based on receipt of a commit signal for each operation, wherein the commit signal for a memory reference operation indicates the apparent completion of the operation rather than actual completion of the operation. In addition, the IOP comprises a prefetch controller coupled to an I/O cache for prefetching data into cache without any ordering constraints (or out-of-order). The ordered retirement functions of the IOP are separated from its prefetching operations, which enables the latter operations to be performed in an arbitrary manner so as to improve the overall performance of the system.

Abstract translation: 改进的I / O处理器（IOP）提供高I / O性能，同时在由共享存储器多处理器系统中的一致性模型指定的I / O设备发出的存储器参考操作之间保持参考间排序。 IOP包括退出控制器，其基于对每个操作的提交信号的接收，在操作之间施加参考间排序，其中用于存储器参考操作的提交信号指示操作的明显完成，而不是实际完成操作。 此外，IOP包括耦合到I / O缓存的预取控制器，用于将数据预取到高速缓存中，而没有任何排序限制（或无序）。 IOP的有序退休功能与其预取操作分离，这使得后面的操作能够以任意方式执行，从而提高系统的整体性能。

公开(公告)号：US6061794A

公开(公告)日：2000-05-09

申请号：US940551

申请日：1997-09-30

Applicant: Michael F. Angelo ,  Sompong P. Olarig ,  David R. Wooten ,  Dan J. Driscoll

Inventor： Michael F. Angelo ,  Sompong P. Olarig ,  David R. Wooten ,  Dan J. Driscoll

IPC: G06F1/00 ,  G06F21/00 ,  G06F12/14

CPC classification number: G06F21/6218 ,  G06F21/606 ,  G06F21/85 ,  G06F2211/007 ,  G06F2221/2141

Abstract: A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligent storage devices and/or controllers, communications devices, video devices and audio devices. The I/O devices perform peer-to-peer message and data transfers, thereby bypassing the operating system running on the computer's CPU. The intelligent I/O devices encrypt messages and data before transmitting them on the I/O bus and conversely decrypt the messages and data upon reception. The encryption provides secrecy and/or authentication of the sender. The devices use keys or passwords to encrypt/decrypt the data. The keys are stored in non-volatile memory in the devices and are distributed to the devices by the system BIOS at initialization time. The devices perform access authorization validation using rule sets also distributed by the BIOS at initialization time. The rule sets specify which I/O operations are valid for a peer I/O device to request of a respective I/O device based, preferably, upon the device class/subclasses of the requesting device. In another embodiment, one of the intelligent I/O devices may be a communications device which serves as a firewall for the I/O bus. In this embodiment, the rule set further includes identification information of the remote machines/devices.

Abstract translation: 用于在诸如PCI总线，光纤通道总线，IEEE，1394总线或通用串行总线的I / O总线上执行安全的对等设备通信的系统和方法。 该系统包括多个智能I / O设备，诸如智能存储设备和/或控制器，通信设备，视频设备和音频设备。 I / O设备执行对等消息和数据传输，从而绕过计算机CPU上运行的操作系统。 智能I / O设备在I / O总线上传输消息和数据之前加密消息和数据，并在接收时反向解密消息和数据。 加密提供发送者的保密和/或认证。 设备使用密钥或密码来加密/解密数据。 密钥存储在设备的非易失性存储器中，并在初始化时由系统BIOS分发给设备。 这些设备使用在BIOS初始化时分配的规则集执行访问授权验证。 规则集指定哪个I / O操作对于对等I / O设备有效，以优选地基于请求设备的设备类/子类来请求相应的I / O设备。 在另一个实施例中，智能I / O设备中的一个可以是用作I / O总线的防火墙的通信设备。 在该实施例中，规则集还包括远程机器/设备的识别信息。

公开(公告)号：US6052134A

公开(公告)日：2000-04-18

申请号：US995705

申请日：1997-12-22

Applicant: Joseph E. Foster

Inventor： Joseph E. Foster

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0215

Abstract: A computer is provided having a memory system supporting page mode accessing. A memory controller may be provided in a bus interface unit coupled between a CPU bus, and a mezzanine bus, or PCI bus. The memory controller includes logic that provides for dynamic management of page accessing. The memory controller may include logic for monitoring the page hit:precharge ratio for accesses to system memory and dynamically switch between a paging state of operation and an auto-precharge state of operation according to the hit:precharge ratio. A configuration register may be provided to select dynamic mode in which the memory controller dynamically enables/disables paging to improve performance. The configuration register may also be programmed to manually enable/disable paging. The memory controller may include a page table for tracking open pages. The system memory may include SDRAM devices.

Abstract translation: 提供了具有支持页面模式访问的存储器系统的计算机。 可以在耦合在CPU总线和夹层总线或PCI总线之间的总线接口单元中提供存储器控制器。 存储器控制器包括提供页面访问的动态管理的逻辑。 存储器控制器可以包括用于监视页面命中的逻辑：用于访问系统存储器的预充电比例，并根据命中：预充电比动态地在寻呼操作状态和自动预充电状态之间切换。 可以提供配置寄存器以选择动态模式，其中存储器控制器动态地启用/禁用寻呼来提高性能。 也可以将配置寄存器编程为手动启用/禁用寻呼。 存储器控制器可以包括用于跟踪打开页面的页表。 系统存储器可以包括SDRAM设备。

公开(公告)号：US5978233A

公开(公告)日：1999-11-02

申请号：US99585

申请日：1998-06-18

Applicant: Brett D. Roscoe ,  George D. Megason ,  Joseph R. Allen

Inventor： Brett D. Roscoe ,  George D. Megason ,  Joseph R. Allen

IPC: H05K7/14 ,  B65D85/86

CPC classification number: H05K7/1409

Abstract: An apparatus is provided for coupling a printed circuit board within a printed circuit board cage. The apparatus includes a baseplate and a latch. The baseplate is mounted to the printed circuit board. The latch is rotably coupled to the baseplate. The latch includes a pivoting portion, a shaft, and a swell nut. The pivoting portion includes an ejector extending from an end of the pivoting portion. The ejector is engageable with the printed circuit board cage. The shaft is coupled to the pivoting portion. The swell nut is coupled to the shaft and engageable with the printed circuit board cage.

Abstract translation: 提供一种用于将印刷电路板耦合在印刷电路板保持架内的装置。 该装置包括底板和闩锁。 底板安装到印刷电路板上。 闩锁可旋转地联接到基板。 闩锁包括枢转部分，轴和膨胀螺母。 枢转部分包括从枢转部分的端部延伸的喷射器。 喷射器可与印刷电路板保持架接合。 轴联接到枢转部分。 膨胀螺母联接到轴上并可与印刷电路板保持架接合。

公开(公告)号：US5959841A

公开(公告)日：1999-09-28

申请号：US777816

申请日：1996-12-31

Applicant: Joseph R. Allen ,  B. Tod Cox ,  James P. Shero

Inventor： Joseph R. Allen ,  B. Tod Cox ,  James P. Shero

IPC: G06F1/18 ,  G06F1/16 ,  H05K5/00

CPC classification number: G06F1/185 ,  G06F1/181 ,  G06F1/184 ,  G06F1/186

Abstract: A modular computer chassis configurable for both rack mounting and free standing use includes a housing with a multiple compartments for receiving computer devices and peripherals therein. The housing further includes side access panels and a top access panel, each being attachable and removable from the frame of the chassis without tools. The frame of the modular computer chassis is configured with slots to receive corresponding tabs on each of the side and top panels which facilitate the quick installation and removal of the side and top panels from the frame of the chassis. Multiple tool-less fasteners are used to further secure side and top covers to the frame of the chassis.

Abstract translation: 可配置用于机架安装和独立使用的模块化计算机机箱包括具有用于在其中接收计算机设备和外围设备的多个隔间的壳体。 壳体还包括侧面检修面板和顶部检修面板，每个面板均可从机架的框架上拆卸而不用工具。 模块化计算机机箱的框架配置有槽，以在每个侧板和顶板上接收相应的突片，这有助于从底架的框架快速安装和移除侧板和顶板。 多个无工具的紧固件用于将侧盖和顶盖进一步固定到机架的框架上。