公开(公告)号：US20020078111A1

公开(公告)日：2002-06-20

申请号：US10014575

申请日：2001-12-14

Inventor： Kozo Mugishima

IPC: G06F001/02

CPC classification number: G06F7/68 ,  G06F1/0328

Abstract: In order to generate a multiple of a unit U, N times U, by a digital circuit is provided, where U is a rational number and N is a natural number, the method comprises the following steps (1) to (5). (1) Where A, B and C are natural numbers, A>1, B>C and UnullAnullC/B, the values A, B and C are stored. (2) A multiple of A, N times A and a multiple of C, N times C are generated. (3) The multiple of C is compared with the denominator B. (4) The multiple of A is modified according to the result of the comparing step (3). (5) The modified multiple of A is output as the multiple of U.

Abstract translation: 为了产生单元U的倍数，通过数字电路提供N次U，其中U是有理数，N是自然数，该方法包括以下步骤（1）至（5）。 （1）其中A，B和C为自然数，A> 1，B> C，U = A + C / B，存储值A，B和C。 （2）A的倍数，N次A，C的倍数，N次C。 （3）将C的倍数与分母B进行比较。（4）根据比较步骤（3）的结果修改A的倍数。 （5）A的修正倍数以U的倍数输出

公开(公告)号：US20020008588A1

公开(公告)日：2002-01-24

申请号：US09867829

申请日：2001-05-30

Inventor： Nasserullah Khan

IPC: H03B021/00 ,  H03L007/08 ,  H03L007/18

CPC classification number: H03L7/16 ,  G06F1/0328 ,  H03B21/00 ,  H03L7/18

Abstract: A direct digital frequency synthesizer and a hybrid frequency synthesizer combining the direct digital frequency synthesizer and a phase locked loop is provided. The direct digital frequency synthesizer includes a phase accumulator that is configured to generate a discrete phase signal. Spurious phase modulation in the discrete phase signal is reduced by a noise shaper, and the output of the noise shaper is then used to address a phase-to-amplitude translator. The phase-to-amplitude translator generates a discrete waveform which is converted to a continuous waveform by a digital to analog converter. The hybrid frequency synthesizer uses a mixer to combine a reference frequency generated by a reference source and a DDFS output signal generated by a direct digital frequency synthesizer. The output from the mixer is then coupled to the input of a phase locked loop which multiplies the mixer output to generate the frequency synthesizer output.

Abstract translation: 提供了直接数字频率合成器和组合直接数字频率合成器和锁相环的混合频率合成器。 直接数字频率合成器包括被配置为产生离散相位信号的相位累加器。 离散相位信号中的杂散相位调制由噪声整形器降低，然后使用噪声整形器的输出来寻址相位到幅度的转换器。 相位到幅度的转换器产生一个离散的波形，通过一个数模转换器转换成一个连续的波形。 混合频率合成器使用混频器来组合由参考源产生的参考频率和由直接数字频率合成器产生的DDFS输出信号。 混频器的输出然后耦合到锁相环的输入端，该锁相环将混频器输出相乘以产生频率合成器输出。

公开(公告)号：US5977804A

公开(公告)日：1999-11-02

申请号：US905661

申请日：1997-08-04

Applicant: Brian Herbert Beech

Inventor： Brian Herbert Beech

IPC: G06F1/03 ,  H03L7/18 ,  H03B19/00

CPC classification number: G06F1/0328 ,  H03L7/1806 ,  G06F2211/902

Abstract: The invention concerns a method and apparatus to synthesize a frequency employing digital phase words to represent successive phase values. A digital dither signal generator is used to generate a succession of dither words which are summed with the phase words to form address words. The address words are used to address a store to convert the address words to waveform values. The periodic quantisation noise introduced by the digital process is made more random by means of the dither words thereby reducing the quantisation noise components while accepting an increased total noise power. The synthesizer is of particular advantage when used to generate the reference frequency for a frequency multiplier implemented as a phase lock loop. By making the dither sequence repetition frequency outside the phase lock loop bandwidth, the spurious components are removed from the frequency range of interest.

Abstract translation: 本发明涉及一种使用数字相位字来合成频率来表示连续相位值的方法和装置。 数字抖动信号发生器用于产生与相位字相加的一连串抖动字以形成地址字。 地址字用于寻址存储以将地址字转换为波形值。 由数字处理引入的周期性量化噪声通过抖动字进行更随机，从而在接受增加的总噪声功率的同时减少量化噪声分量。 当用于为实现为锁相环的倍频器生成参考频率时，合成器具有特别的优点。 通过使抖动序列重复频率超出锁相环带宽，则从感兴趣的频率范围中去除杂散分量。

公开(公告)号：US5936438A

公开(公告)日：1999-08-10

申请号：US941959

申请日：1997-10-01

Applicant: J. William Whikehart ,  Bradley Anderson Ballard

Inventor： J. William Whikehart ,  Bradley Anderson Ballard

IPC: G06F1/03 ,  H03B21/00

CPC classification number: G06F1/0328

Abstract: A digital waveform oscillator generates digitized waveforms without distortion using a lookup table. The frequencies which may be generated using direct lookup tables at their fundamental table frequencies are increased according to this invention by including multiple cycles of the waveform within a single table. The selection of a table length L and a number of cycles N to be stored in a lookup table is done in a manner to optimize corresponding values of the frequencies to be generated and the sample rate.

Abstract translation: 数字波形振荡器使用查找表生成无畸变的数字化波形。 根据本发明，可以通过在单个表格内包括波形的多个周期来增加在其基本频率下使用直接查找表产生的频率。 以存储在查找表中的表长度L和周期数N的选择以优化要生成的频率的相应值和采样率的方式完成。

公开(公告)号：US5459680A

公开(公告)日：1995-10-17

申请号：US141295

申请日：1993-10-20

Applicant: George A. Zimmerman ,  Michael J. Flanagan

Inventor： George A. Zimmerman ,  Michael J. Flanagan

IPC: G06F1/03 ,  G06F1/02

CPC classification number: G06F1/0328 ,  G06F2211/902

Abstract: A technique for reducing the spurious signal content in digital sinusoid synthesis. Spur reduction is accomplished through dithering both amplitude and phase values prior to word-length reduction. The analytical approach developed for analog quantization is used to produce new bounds on spur performance in these dithered systems. Amplitude dithering allows output word-length reduction without introducing additional spurs. Effects of periodic dither similar to that produced by pseudo-noise (PN) generator are analyzed. This phase dithering method provides a spur reduction of 6(M+1) dB per phase bit when the dither consists of M uniform variates. While the spur reduction is at the expense of an increase in system noise, the noise power can be made white, making the power spectral density small. This technique permits the use of a smaller number of phase bits addressing sinusoid look-up tables, resulting in an exponential decrease in system complexity. Amplitude dithering allows the use of less complicated multipliers and narrower data paths in purely digital applications, as well as the use of coarse-resolution, highly-linear digital-to-analog converters (DACs) to obtain spur performance limited by the DAC linearity rather than its resolution.

Abstract translation: 一种用于减少数字正弦波合成中杂散信号含量的技术。 通过在字长减小之前抖动振幅和相位值来实现支路减小。 用于模拟量化的分析方法用于在这些抖动系统中产生杂散性能的新界限。 幅度抖动允许输出字长减少而不引入额外的杂散。 分析类似于由伪噪声（PN）发生器产生的周期抖动的影响。 当抖动由M个均匀变量组成时，该相位抖​​动方法提供每相位位6（M + 1）dB的杂散减少。 虽然减少刺激是以系统噪声增加为代价的，但噪声功率可以变为白色，使功率谱密度较小。 该技术允许使用较少数量的相位位来解决正弦曲线查找表，导致系统复杂度的指数下降。 幅度抖动允许在纯数字应用中使用较不复杂的乘法器和更窄的数据路径，以及使用粗分辨率，高线性数模转换器（DAC）来获得受DAC线性度限制的支线性能， 比其决议。

公开(公告)号：US5424739A

公开(公告)日：1995-06-13

申请号：US171485

申请日：1993-12-21

Applicant: Steven R. Norsworthy ,  Rich: David A. ,  Thayamkulangara R. Viswanathan

Inventor： Steven R. Norsworthy ,  Rich: David A. ,  Thayamkulangara R. Viswanathan

IPC: H03M1/08 ,  G06F1/03 ,  H03M3/02 ,  H03M3/04 ,  H03M7/36 ,  H04B14/04 ,  H03M3/00

CPC classification number: H03M7/3042 ,  G06F1/0328 ,  H04B14/046 ,  H03M7/3026

Abstract: A device for digitally shaping the quantization noise of an N-bit digital signal, N being a positive integer, comprises: a register for masking out selected bits of the N-bit digital signal to produce an M-bit digital signal, M being a positive integer less than N; a digital noise-shaping coder, coupled to the register, for shaping the quantization noise of the masked out bits; and an accumulator, coupled to the register and the coder, for accumulating the digital signals received from the register and the coder. Likewise, a method of digitally shaping the quantization noise of an N-bit digital signal, N being a positive integer, comprises the steps of: masking selected bits of an N-bit digital signal to produce an M-bit digital signal, M being a positive integer less than N; digitally coding the masked bits of the N-bit digital signal to produce a B-bit digital signal, B being a positive integer less than N-M; and accumulating the M-bit digital signal and the B-bit digital signal.

Abstract translation: 一种用于数字整形N位数字信号的量化噪声的装置，N是正整数，包括：用于掩蔽N位数字信号的选定位以产生M位数字信号的寄存器，M为 小于N的正整数; 数字噪声整形编码器，耦合到寄存器，用于对掩蔽出的位的量化噪声进行整形; 以及耦合到寄存器和编码器的累加器，用于累加从寄存器和编码器接收的数字信号。 同样地，对N位数字信号（N为正整数）的量化噪声进行数字整形的方法包括以下步骤：屏蔽N位数字信号的选定位以产生M位数字信号，M为 小于N的正整数; 对N位数字信号的屏蔽位进行数字编码以产生B位数字信号，B为小于N-M的正整数; 并累积M位数字信号和B位数字信号。

公开(公告)号：US5231598A

公开(公告)日：1993-07-27

申请号：US769940

申请日：1991-09-30

Applicant: Harry Vlahos

Inventor： Harry Vlahos

IPC: G01R31/319 ,  G01R31/317 ,  G01R31/3193 ,  G04F10/00 ,  G06F1/03

CPC classification number: G04F10/00 ,  G01R31/31725 ,  G01R31/31937 ,  G06F1/0328

Abstract: A skew tester (60) measures output timing skew parameters OSHL and OSLH between multiple output signals of an integrated circuit (IC) device under test (DUT) having an input and multiple outputs. A measurement signal generating circuit (15,16,18,20) generates a square wave measurement signal at a test signal frequency synchronized with a clock signal. The measurement signal generating circuit uses direct digital synthesis to provide a specified phase shift resolution. A test signal generating circuit (15,22,24) generates a square wave test signal at the test signal frequency using the same clock signal. The test signal and measurement signal are therefore synchronized in frequency. The test signal is applied to the input of a DUT (25) and a switch (30) selects one of the DUT output signals. The selected output signal and the square wave measurement signal are applied to the inputs of a comparator (45) which generates an output according to the difference in phase between the selected output signal and measurement signal. A threshold detector circuit (50) delivers a count signal in response to an output from the comparator (45) related to a threshold level. A programmable controller (12) is programmed to shift the phase of the measurement signal toward the phase of the selected output signal in phase increments or steps equal to the specified phase shift resolution during occurrence of count signals. The microcontroller counts phase shift increments to a maximum count (MAXCOUNT) at which the phase of corresponding edges substantially coincide and generates a skew number for comparison with skew numbers from the other multiple outputs and for calculating skew parameters OSHL and OSLH.

Abstract translation: 偏斜测试器（60）测量具有输入和多个输出的被测试集成电路（IC）设备（DUT）的多个输出信号之间的输出定时偏移参数OSHL和OSLH。 测量信号产生电路（15,16,18,20）以与时钟信号同步的测试信号频率产生方波测量信号。 测量信号发生电路使用直接数字合成来提供规定的相移分辨率。 测试信号发生电路（15,22,24）使用相同的时钟信号在测试信号频率下产生方波测试信号。 因此，测试信号和测量信号在频率上同步。 测试信号被施加到DUT的输入端（25），开关（30）选择一个DUT输出信号。 所选择的输出信号和方波测量信号被施加到比较器（45）的输入，比较器（45）根据所选择的输出信号和测量信号之间的相位差产生输出。 阈值检测器电路（50）响应于与阈值电平相关的来自比较器（45）的输出传送计数信号。 可编程控制器（12）被编程为在计数信号发生期间以相位增量或等于指定的相移分辨率的方式将测量信号的相位移向所选输出信号的相位。 微控制器将相移增量计算到最大计数（MAXCOUNT），在此最大计数（MAXCOUNT）处，相应边沿的相位基本上重合，并产生一个偏斜数，用于与来自其他多个输出的偏移数进行比较，并用于计算偏差参数OSHL和OSLH。

公开(公告)号：US5216389A

公开(公告)日：1993-06-01

申请号：US828829

申请日：1992-01-31

Applicant: Cesar W. Carralero ,  Jaime A. Borras ,  Armando J. Gonzalez

Inventor： Cesar W. Carralero ,  Jaime A. Borras ,  Armando J. Gonzalez

IPC: G06F1/03 ,  H03L1/02 ,  H03L7/18

CPC classification number: H03L1/026 ,  H03L7/1806 ,  G06F1/0328

Abstract: Certain operational characteristics of a crystal (104) are measured during a testing and grading process. Once determined, information representing these operational characteristics are stored in memory (120) and utilized by a controller (122) to increment a phase increment register (114) upon determining the crystals ambient temperature via a temperature sensing circuit (124). The value stored in the phase increment register (114) is then sent to a phase accumulator (116) where successive phase increments are summed together. This summed value is in turn sent to a sine lookup table (118) where the instantaneous phase value is converted into sine amplitude. Finally, a digital to analog converter (126) converts the amplitude bit stream into an analog signal for use as a reference oscillator frequency having extremely high frequency resolution. The above mentioned process is repeated every clock cycle until a complete sine wave is produced at which point the phase accumulator is reset to zero and the process begins again.

Abstract translation: 在测试和分级过程中测量晶体（104）的某些操作特性。 一旦确定，表示这些操作特性的信息被存储在存储器（120）中，并由控制器（122）利用，以在通过温度检测电路（124）确定晶体环境温度之后递增相位增量寄存器（114）。 存储在相位增量寄存器（114）中的值然后被发送到相位累加器（116），其中连续的相位增量被相加在一起。 该总和值又被发送到正弦查找表（118），其中瞬时相位值被转换成正弦幅度。 最后，数模转换器（126）将振幅比特流转换为模拟信号，以用作具有极高频率分辨率的参考振荡器频率。 每个时钟周期重复上述过程，直到产生完整的正弦波，在该点将相位累加器复位到零，并且该过程再次开始。

公开(公告)号：US5153526A

公开(公告)日：1992-10-06

申请号：US704360

申请日：1991-05-23

Applicant: Katsuya Hori ,  Eiichiro Morinaga

Inventor： Katsuya Hori ,  Eiichiro Morinaga

IPC: G06F1/03 ,  H03B28/00 ,  H03L7/099

CPC classification number: H03L7/0994 ,  G06F1/0328

Abstract: A numerical control type oscillator whose output oscillation frequency is controlled depending on input numerical data, comprises: first accumulation means for accumulating a first set value which is set depending on the input numerical data with a first frequency and sequentially outputting the accumulated value; second accumulation means for accumulating a second set value which is set depending on the input numerical data with a second frequency and varying the first set value by a predetermined value temporarily when the accumulated value reaches a predetermined maximum value; and frequency generation means for outputting a frequency depending on an output of the first accumulation means as an oscillation frequency.

公开(公告)号：US5014231A

公开(公告)日：1991-05-07

申请号：US380786

申请日：1989-07-17

Applicant: Victor S. Reinhardt ,  Kim V. Gould ,  Kevin M. McNab

Inventor： Victor S. Reinhardt ,  Kim V. Gould ,  Kevin M. McNab

IPC: G06F1/03

CPC classification number: G06F1/0328 ,  G06F2211/902

Abstract: A sine output or phase interpolation direct digital synthesizer for use in satellite programs having a random or pseudorandom code generator for summing a random digital word whose value ranges from zero to just under the least significant bit of a digital-to-analog converter with the current register value normally sent to the converter for reducing the spurious sidebands associated with the finite resolution of the converter within the synthesizer, the sum being truncated to the resolution of the converter and for controlling the converter, the spurious sidebands being reduced by randomization of the periodic behavior associated with the truncation process while lowering the total phase noise.

Abstract translation: 正弦输出或相位插值直接数字合成器，用于具有随机或伪随机码发生器的卫星程序中，用于将数值范围从零到刚好在具有当前数字 - 模拟转换器的最低有效位之间的随机数字字 通常发送到转换器的寄存器值用于减少与合成器内的转换器的有限分辨率相关联的寄生边带，该和被截断到转换器的分辨率并用于控制转换器，通过周期性的随机化来减少杂散边带 降低总相位噪声时与截断过程相关的行为。