公开(公告)号：US20190095303A1

公开(公告)日：2019-03-28

申请号：US16198299

申请日：2018-11-21

申请人： The MathWorks, Inc.

发明人： Kiran K. Kintali ,  Shomit Dutta ,  E. Mehran Mestchian ,  Pieter J. Mosterman

IPC分类号： G06F11/26 ,  G06F17/50 ,  G06F7/483

摘要： Systems and methods evaluate simulation models and measure floating point arithmetic errors in terms of Unit in Last Place (ULP). The simulation model may include model elements that perform numerical computations using Native Floating Point (NFP) arithmetic. The model elements may be arranged to implement a procedure. A data store may include local ULP errors predetermined for the model elements. The systems and methods may retrieve the local ULP errors for the model elements included in the model, and may apply a rules-based analysis to compute an overall ULP error of the simulation model. The systems and methods may present the overall ULP computed for the model. The systems and methods may also present intermediate ULP errors determined for portions of the simulation model. Changes may be made to the model to reduce the overall ULP error.

公开(公告)号：US10241888B2

公开(公告)日：2019-03-26

申请号：US14082543

申请日：2013-11-18

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Ralf Schaufler ,  Tobias Senner

IPC分类号： G06F11/34 ,  G06F11/36 ,  G06F11/26

摘要： A method is presented to verify correctness of computer system software and hardware components. The method includes: operating a test environment with a verified system software and hardware version; monitoring and recording each hardware access during operation of the test environment with the verified system software and hardware version to generate a corresponding verified trace file; operating the test environment with a modified system software and/or hardware version; monitoring and recording each hardware access to generate a corresponding new trace file during operation of the test environment with the modified system software and/or hardware version; defining an arbitrary order for target chips in the verified and the modified hardware model or hardware system version; sorting sequences of entries in both trace files according to the target chip order; and comparing the sorted trace files by comparing their entries each by each and outputting a corresponding comparison result.

公开(公告)号：US20190079849A1

公开(公告)日：2019-03-14

申请号：US16077899

申请日：2016-02-17

申请人： ENTIT SOFTWARE LLC

发明人： Amitay Korn ,  Avivi Siman-Tov ,  Olga Kogan

IPC分类号： G06F11/34 ,  G06F11/36 ,  G06F11/26

摘要： Example implementations relate to simulating an environment. For example, a system for environment simulation may include a simulation engine to build an environment simulation to mimic portions of a real environment relevant to a detected anomaly trend, an acceleration engine to simulate, within the environment simulation, a scenario associated with the detected anomaly at a rate faster than the scenario occurs in the real environment, a abnormal behavior engine to detect a abnormal behavior associated with the scenario, and an adaptation engine to modify a device within the real environment to be adaptive to the scenario, based on the detected abnormal behavior.

公开(公告)号：US10223224B1

公开(公告)日：2019-03-05

申请号：US15194464

申请日：2016-06-27

申请人： EMC Corporation

发明人： Charles Hickey ,  Alice Cuicui Zhao ,  Jose Medina

IPC分类号： G06F11/00 ,  G06F11/26 ,  G06F3/06

摘要： According to one embodiment, a test result of a first disk that was removed from a storage system and tested at a remote testing facility is received. A data analysis is performed on operational statistics data associated with the first disk based on one or more predetermined data patterns, where the operational statistics data was periodically collected from the storage system during operations of the storage system. A failure category of the first disk is determined based on the data analysis by comparing the operational statistics data against the predetermined data patterns. At least one of the data patterns is adjusted for subsequent determination of failure categories in view of an analysis result of the analysis, the failure category, and the testing result received from the testing facility.

公开(公告)号：US20190050314A1

公开(公告)日：2019-02-14

申请号：US16141971

申请日：2018-09-26

申请人： International Business Machines Corporation

发明人： Manoj Dusanapudi ,  Shakti Kapoor ,  Nelson Wu

IPC分类号： G06F11/30 ,  G06F12/1081 ,  G06F13/28 ,  G06F13/10 ,  G06F11/26 ,  G06F11/263 ,  G06F11/22

摘要： A circuit and method provide efficient stress testing of address translations in an integrated circuit such as a link processing unit. A random DMA mode (RDM) circuit provides a random input to index into a translation validation table (TVT) that is used to generate the real memory address. The RDM circuit allows testing all entries of the TVT, and thus all DMA modes, regardless of what bus agents are connected to the link processing unit. The RDM circuit may use a multiplexer to select between a runtime input and a random test input provided by the random bit generator. When the link processing unit is in a test mode a mode selection bit is asserted to select the random test input.

公开(公告)号：US20190050307A1

公开(公告)日：2019-02-14

申请号：US16140496

申请日：2018-09-24

申请人： Intel Corporation

发明人： Kevin Locker ,  Sai Ram Dheeraj Lokam ,  Siva Prasad Kota ,  Massimo Ceppi ,  Teo Cupaiuolo

IPC分类号： G06F11/26 ,  G06F17/50 ,  G01R31/00

摘要： Embodiments include apparatuses, methods, and systems for testing an IC of an in-vehicle system of a CA/AD vehicle includes a storage device and processing circuitry coupled with the storage device. A gate level fault group is provided to include one or more gate level faults of a fault model associated to a gate level circuit element of the gate level netlist of the IC with substantially same fault controllability or observability characteristics. A correlated RTL fault group is determined to be associated to a RTL circuit node, where the RTL circuit node of the RTL netlist corresponds to the gate level circuit element. Other embodiments may also be described and claimed.

公开(公告)号：US20190026204A1

公开(公告)日：2019-01-24

申请号：US15652763

申请日：2017-07-18

申请人： The Boeing Company

发明人： Jonathan N. HOTRA

IPC分类号： G06F11/26

摘要： Methods and systems are provided for testing a physical hardware device by a virtual hardware device using a virtualization system. The methods and systems perform operations including determining a memory location of a variable through which the virtual hardware device exchanges information with an external hardware resource. The operations also include exchanging the information with the external hardware resource via the memory location of the variable. The memory location of the variable used by the virtual hardware device is the same as a memory location of the variable used by the physical hardware device.

公开(公告)号：US20190018748A1

公开(公告)日：2019-01-17

申请号：US16069057

申请日：2016-01-13

申请人： ENTIT SOFTWARE LLC

发明人： Inbar Shani ,  Eli Mordechai ,  Jonathan Taragin ,  Iris Sasson

IPC分类号： G06F11/26

摘要： Example implementations relate to determining a functional state of a system under test. For example, a system to determine a functional state of a system under test may include a system controller to execute a functional test of the system under test by invoking a subset of a plurality of functional agents to interact with the system under test. Further, the system may include an agent repository to interact with the system controller and store the plurality of functional agents. Also, the system may include a state module to determine a functional state for the system under test by querying each of the subset of functional agents and comparing aggregated results from the subset of functional agents against defined for the system under test.

公开(公告)号：US20190012247A1

公开(公告)日：2019-01-10

申请号：US15643356

申请日：2017-07-06

申请人： Sorenson IP Holdings, LLC

发明人： Jeffrey Bullough

IPC分类号： G06F11/26 ,  G06F11/22

CPC分类号： G06F11/26 ,  G06F11/2236

摘要： According to one or more aspects of the present disclosure, operations may include activating testing software of a digital signal processing system instead of activating operating software of the digital signal processing system. The testing software may be configured to, while activated, perform linear operations with respect to signals that traverse the signal path. The operating software may be configured to, while activated, perform non-linear operations with respect to signals that traverse the signal path. The testing software may be activated during testing of one or more hardware elements of the signal path that are configured to perform analog operations on signals that traverse the signal path.

公开(公告)号：US10176032B2

公开(公告)日：2019-01-08

申请号：US14732285

申请日：2015-06-05

申请人： Uptake Technologies, Inc.

发明人： Michael Horrell ,  John Ciasulli ,  Sheng Zhong ,  Adam McElhinney ,  Brian Silva

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06Q10/00 ,  G06F11/26 ,  G06F11/263 ,  G08B21/18 ,  G01D3/08 ,  G01M99/00 ,  G06F11/20 ,  G06N5/02 ,  G06N7/00 ,  H04L12/707 ,  G06Q10/06 ,  G06N5/04 ,  G06Q10/04

摘要： Disclosed herein are systems, devices, and methods related to assets and asset operating conditions. In particular, examples involve defining and executing predictive models for outputting health metrics that estimate the operating health of an asset or a part thereof, analyzing health metrics to determine variables that are associated with high health metrics, and modifying the handling of abnormal-condition indicators in accordance with a prediction of a likely response to such abnormal-condition indicators, among other examples.