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公开(公告)号：US20100046270A1
公开(公告)日：2010-02-25
申请号：US12514025
申请日：2007-11-16
CPC分类号： G11C13/003 , G11C11/5685 , G11C13/0007 , G11C13/0069 , G11C2013/009 , G11C2213/31 , G11C2213/32 , G11C2213/76 , G11C2213/79
摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.
摘要翻译： 本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定 单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位 在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大 在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。
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102.发明授权Computer systems and methods for subdividing a complex disease into component diseases 有权将复杂疾病细分为成分疾病的计算机系统和方法公开(公告)号：US07653491B2
公开(公告)日：2010-01-26
申请号：US10515804
申请日：2003-05-20
申请人： Eric E. Schadt , Stephanie A. Monks
发明人： Eric E. Schadt , Stephanie A. Monks
摘要： A method for identifying a quantitative trait loci for a complex trait that is exhibited by a plurality of organisms in a population. The population is divided into a plurality of sub-populations using a classification scheme. Depending on what is known about the population, either a supervised or unsupervised classification is used. The classification scheme is derived from a plurality of cellular constituent measurements obtained from each organism in the population. For each sub-population in the plurality of sub-populations, a quantitative genetic analysis is performed on the sub-population in order to identify one or more quantitative trait loci for the complex trait.
摘要翻译： 用于鉴定由群体中的多种生物体展现的复杂性状的数量性状位点的方法。 使用分类方案将群体分成多个子群体。 根据已知的人口，使用监督或无监督分类。 分类方案来源于从群体中的每个生物获得的多个细胞成分测量。 对于多个子群体中的每个子群体，对子群体进行定量遗传分析，以便鉴定复杂性状的一个或多个数量性状位点。
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公开(公告)号：US20090323389A1
公开(公告)日：2009-12-31
申请号：US12106927
申请日：2008-04-21
申请人： THOMAS KUENEMUND , Karl Zapf , Artur Wroblewski
发明人： THOMAS KUENEMUND , Karl Zapf , Artur Wroblewski
摘要： An array of masked memory cells including a first memory cell in a first column and a second memory cell in a second different column, wherein the first memory cell is capable of being accessed, so as to output, dependent on a first binary mask signal, a first binary value at a first output and a second binary value at a second output or vice versa, wherein the second memory cell is capable of being accessed, so as to output, dependent on a second binary mask signal, a first binary value at a third output and a second binary value at a fourth output or vice versa, and wherein the second and the third outputs of the memory cells are connected to an identical bit line of the memory array.
摘要翻译： 一种掩蔽存储单元的阵列，包括第一列中的第一存储单元和第二不同列中的第二存储单元，其中第一存储单元能够被访问，以便根据第一二进制掩码信号输出， 在第一输出处的第一二进制值和第二输出处的第二二进制值，反之亦然，其中第二存储器单元能够被访问，以便根据第二二进制掩码信号输出第二二进制值 第三输出和第二二进制值在第四输出或反之亦然，并且其中存储器单元的第二和第三输出连接到存储器阵列的相同位线。
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公开(公告)号：US20090316464A1
公开(公告)日：2009-12-24
申请号：US12488624
申请日：2009-06-22
申请人： Ashish Sharma , Sanjeev Kumar Jain , Manmohan Rana
发明人： Ashish Sharma , Sanjeev Kumar Jain , Manmohan Rana
摘要： A ROM includes a ROM array, an address decoder, a control circuit, a precharge tracker, a precharge circuit, a reference word line, a reference bit line and a reference sense generator. The control circuit generates control signals for reading the ROM. The address decoder enables a bit line and a word line. The precharge tracker generates a programmable precharge signal, which is provided to the precharge circuit for precharging the enabled bit line. A reference word line is enabled based on the programmable precharge signal and the control signals for tracking the enabled word line. A reference bit line is enabled based on the reference word line for tracking the enabled bit line. The reference sense generator generates a programmable sense signal based on the reference bit line, the programmable precharge signal and the control signals for reading a bit cell corresponding to the enabled bit line and word line.
摘要翻译： ROM包括ROM阵列，地址解码器，控制电路，预充电跟踪器，预充电电路，参考字线，参考位线和参考检测发生器。 控制电路产生用于读取ROM的控制信号。 地址解码器支持位线和字线。 预充电跟踪器产生可编程预充电信号，该预充电信号被提供给预充电电路，用于预充电使能的位线。 基于可编程预充电信号和用于跟踪使能字线的控制信号使能参考字线。 基于用于跟踪使能的位线的参考字线使能参考位线。 参考检测发生器基于参考位线，可编程预充电信号和用于读取对应于使能位线和字线的位单元的控制信号产生可编程感测信号。
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公开(公告)号：US20090303769A1
公开(公告)日：2009-12-10
申请号：US12136400
申请日：2008-06-10
CPC分类号： G11C7/18 , G11C11/5692 , G11C17/12 , H01L27/0207 , H01L27/112
摘要： Electronic apparatus, methods of forming the electronic apparatus, and methods of operating the electronic apparatus include a read only memory having a memory array of bit-lines, where the bit-lines are arranged such that each bit-line has a shared arrangement with one or more other bit-lines of the memory array. Each shared arrangement is structured to operably store a plurality of bits.
摘要翻译： 电子设备，电子设备的形成方法以及操作电子设备的方法包括具有位线存储器阵列的只读存储器，其中位线布置成使得每个位线具有与一个位线的共享布置 或更多其他存储器阵列的位线。 每个共享布置被构造为可操作地存储多个位。
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公开(公告)号：US20090262567A1
公开(公告)日：2009-10-22
申请号：US12418822
申请日：2009-04-06
申请人： Chang-Hee SHIN , Ki-Seok CHO
发明人： Chang-Hee SHIN , Ki-Seok CHO
摘要： A nonvolatile memory device including one-time programmable (OTP) unit cell is provided. The nonvolatile memory device includes: a unit cell; a detecting unit configured to detect data from the unit cell; and a read voltage varying unit configured to vary an input voltage and supply a varied read voltage to the unit cell.
摘要翻译： 提供包括一次可编程（OTP）单元的非易失性存储器件。 非易失性存储装置包括：单元电池; 检测单元，被配置为检测来自所述单元的数据; 以及读取电压变化单元，被配置为改变输入电压并向单位单元提供变化的读取电压。
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107.发明申请METHOD OF PROGRAMMING A MEMORY DEVICE OF THE ONE-TIME PROGRAMMABLE TYPE AND INTEGRATED CIRCUIT INCORPORATING SUCH A MEMORY 有权编写一次性可编程类型和集成电路的存储器件的方法，包含这样的存储器公开(公告)号：US20090251942A1
公开(公告)日：2009-10-08
申请号：US12415299
申请日：2009-03-31
申请人： Joel Damien
发明人： Joel Damien
IPC分类号： G11C17/00 , G11C11/416 , G11C5/14 , G05F1/10
CPC分类号： G11C17/16
摘要： A memory device of the irreversibly electrically programmable type is provided with a memory cell having a dielectric zone disposed between a first electrode and second electrode. An access transistor is connected in series with the second electrode, and an auxiliary transistor is connected in series with the first electrode. The auxiliary transistor is biased to have a saturation current which is lower than a saturation current of the access transistor when both the auxiliary and access transistors are actuated. A number of the memory cells are arranged in a memory plane to form the memory device.
摘要翻译： 不可逆电可编程类型的存储器件具有存储单元，该存储单元具有置于第一电极和第二电极之间的介电区。 存取晶体管与第二电极串联连接，辅助晶体管与第一电极串联连接。 当辅助和存取晶体管被致动时，辅助晶体管被偏置为具有低于存取晶体管的饱和电流的饱和电流。 多个存储器单元被布置在存储器平面中以形成存储器件。
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108.发明授权Method, apparatus and system providing a one-time programmable memory device 有权提供一次性可编程存储器件的方法，装置和系统公开(公告)号：US07593248B2
公开(公告)日：2009-09-22
申请号：US11600202
申请日：2006-11-16
申请人： Chen Xu , Thomas W. Voshell , Karl Holtzclaw
发明人： Chen Xu , Thomas W. Voshell , Karl Holtzclaw
IPC分类号： G11C17/00
摘要： Disclosed are apparatus, system and methods of programming and readout of a one-time programmable memory devise having an array of memory cells, where the cells include an anti-fuse element and an in-cell amplifier transistor. Circuitry configured for programming and correlated double sampling readout of the cells is also disclosed.
摘要翻译： 公开了具有存储器单元阵列的一次性可编程存储器设备的编程和读出的装置，系统和方法，其中单元包括反熔丝元件和单元内放大器晶体管。 还公开了配置用于单元的编程和相关双采样读出的电路。
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109.发明申请公开(公告)号：US20090219746A1
公开(公告)日：2009-09-03
申请号：US12297082
申请日：2007-04-12
CPC分类号： G11C17/14
摘要： The circuit arrangement comprises a symmetrically constructed comparator (3), a non-volatile memory cell (10) and a reference element (20). The comparator (3) exhibits a latching function, and is connected in a differential current path that joins the power supply terminal (9) to a reference potential terminal (8). The non-volatile memory cell (10) is connected in a first branch (35) of the differential current path, and the reference element (20) is connected in a second branch (55) of the differential current path.
摘要翻译： 电路装置包括对称构造的比较器（3），非易失性存储单元（10）和参考元件（20）。 比较器（3）具有闭锁功能，并且连接在将电源端子（9）连接到参考电位端子（8）的差动电流通路中。 非易失性存储单元（10）连接在差动电流路径的第一支路（35）中，参考元件（20）连接在差动电流路径的第二支路（55）中。
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公开(公告)号：US07577011B2
公开(公告)日：2009-08-18
申请号：US11623218
申请日：2007-01-15
申请人： Prasad Avss , Ravi Pathakota
发明人： Prasad Avss , Ravi Pathakota
CPC分类号： G11C17/08 , G06F17/5045
摘要： A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.
摘要翻译： 一种用于设计只读存储器（ROM）和相关设备的方法包括将数据集划分成两个或更多个子数据集，每个子数据集具有相同的地址空间，但是具有比原始数据集更小的位宽。 子数据集被折叠，然后提供子数据集的各自的存储单元。 存储单元的输出提供ROM的输出。 每个存储单元包括基于在行折叠期间获得的映射信息将地址映射到字线的解码器，以及由编码子数据集的数据字的解码器驱动的逻辑阵列。
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