公开(公告)号：US20100046270A1

公开(公告)日：2010-02-25

申请号：US12514025

申请日：2007-11-16

申请人： Yoshikazu Katoh ,  Kazuhiko Shimakawa ,  Zhiqiang Wei

发明人： Yoshikazu Katoh ,  Kazuhiko Shimakawa ,  Zhiqiang Wei

IPC分类号： G11C17/00 ,  G11C11/00

CPC分类号： G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/76 ,  G11C2213/79

摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.

摘要翻译： 本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定 单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位 在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大 在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

公开(公告)号：US07920402B2

公开(公告)日：2011-04-05

申请号：US12514025

申请日：2007-11-16

申请人： Yoshikazu Katoh ,  Kazuhiko Shimakawa ,  Zhiqiang Wei

发明人： Yoshikazu Katoh ,  Kazuhiko Shimakawa ,  Zhiqiang Wei

IPC分类号： G11C17/00 ,  G11C11/00

CPC分类号： G11C13/003 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/76 ,  G11C2213/79

摘要： A resistance variable memory apparatus (100) of the present invention is a resistance variable memory apparatus (100) using a resistance variable element (22) transitioning between plural resistance states in response to electric pulses of the same polarity, in which a series resistance setting unit (10) is configured to set a resistance value of the series current path and a parallel resistance setting unit (30) is configured to set a resistance value of a parallel current path such that the resistance values become resistance values at which a node potential is not larger than a second voltage level in a state where an electric pulse application device (50) is outputting a first electric pulse after the resistance variable element (22) has switched to the high-resistance state, and the node potential is not larger than a first voltage level in the state where the electric pulse application device (50) is outputting a second electric pulse after the resistance variable element (22) has switched to the low-resistance state.

摘要翻译： 本发明的电阻可变存储装置（100）是电阻可变存储装置（100），其使用电阻可变元件（22），其响应于相同极性的电脉冲在多个电阻状态之间转变，其中串联电阻设定 单元（10）被配置为设置串联电流路径的电阻值，并联电阻设定单元（30）被配置为设置并联电流路径的电阻值，使得电阻值成为节点电位 在电阻可变元件（22）切换到高电阻状态之后电脉冲施加装置（50）输出第一电脉冲的状态下不大于第二电压电平，并且节点电位不大 在电脉冲施加装置（50）在电阻可变元件（22）之后输出第二电脉冲的状态下的第一电压电平ha s切换到低电阻状态。

公开(公告)号：US20100110766A1

公开(公告)日：2010-05-06

申请号：US12524313

申请日：2008-02-22

申请人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

发明人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC分类号： G11C11/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

摘要翻译： 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

公开(公告)号：US07916516B2

公开(公告)日：2011-03-29

申请号：US12524313

申请日：2008-02-22

申请人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

发明人： Zhiqiang Wei ,  Kazuhiko Shimakawa ,  Takeshi Takagi ,  Yoshikazu Katoh

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/34 ,  G11C2213/72 ,  H01L27/1021

摘要： A nonvolatile memory apparatus comprises a memory array (102) including plural first electrode wires (WL) formed to extend in parallel with each other within a first plane; plural second electrode wires (BL) formed to extend in parallel with each other within a second plane parallel to the first plane and to three-dimensionally cross the plural first electrode wires; and nonvolatile memory elements (11) which are respectively provided at three-dimensional cross points between the first electrode wires and the second electrode wires, the elements each having a resistance variable layer whose resistance value changes reversibly in response to a current pulse supplied between an associated first electrode wire and an associated second electrode wire; and a first selecting device (13) for selecting the first electrode wires, and further comprises voltage restricting means (15) provided within or outside the memory array, the voltage restricting means being connected to the first electrode wires, for restricting a voltage applied to the first electrode wires to a predetermined upper limit value or less; wherein plural nonvolatile memory elements of the nonvolatile memory elements are connected to one first electrode wire connecting the first selecting device to the voltage restricting means.

摘要翻译： 非易失性存储装置包括存储器阵列（102），其包括形成为在第一平面内彼此平行延伸的多个第一电极线（WL） 多个第二电极线（BL），其形成为在与第一平面平行的第二平面内彼此平行延伸并且三维地交叉所述多个第一电极线; 和非易失性存储元件（11），其分别设置在第一电极线和第二电极线之间的三维交叉点处，每个元件具有电阻变化层，其电阻值响应于在 相关联的第一电极线和相关联的第二电极线; 以及用于选择所述第一电极线的第一选择装置（13），并且还包括设置在所述存储器阵列内或外的电压限制装置（15），所述电压限制装置连接到所述第一电极线，用于限制施加到 所述第一电极线达到预定的上限值以下; 其中所述非易失性存储元件的多个非易失性存储元件连接到将所述第一选择装置连接到所述电压限制装置的一个第一电极线。

公开(公告)号：US08094482B2

公开(公告)日：2012-01-10

申请号：US12529466

申请日：2008-10-28

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5646 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value.

摘要翻译： 本发明的非易失性存储装置和非易失性数据存储介质，包括各自根据施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路，其中施加第一电脉冲到 将非易失性存储元件的电阻值从第一电阻值切换到与第一电脉冲极性相反的第二电阻值和第二电脉冲的非易失性存储元件施加到非易失性存储元件，以将电阻 非易失性存储元件的值从第二电阻值到第一电阻值。

公开(公告)号：US20100014343A1

公开(公告)日：2010-01-21

申请号：US12529466

申请日：2008-10-28

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Ken Kawai ,  Kazuhiko Shimakawa

IPC分类号： G11C11/00 ,  G11C11/416

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2211/5646 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： [Objective] A nonvolatile memory apparatus and a nonvolatile data storage medium of the present invention, including nonvolatile memory elements each of which changes its resistance in response to electric pulses applied, comprises a first write circuit (106) for performing first write in which a first electric pulse is applied to the nonvolatile memory element to switch a resistance value of the nonvolatile memory element from a first resistance value to a second resistance value and a second electric pulse which is opposite in polarity to the first electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the second resistance value to the first resistance value; and a second write circuit (108) for performing second write in which a third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from a third resistance value to a fourth resistance value and a fourth electric pulse which is identical in polarity to the third electric pulse is applied to the nonvolatile memory element to switch the resistance value of the nonvolatile memory element from the fourth resistance value to a fifth resistance value.

摘要翻译： [目的]本发明的非易失性存储装置和非易失性数据存储介质，包括响应于施加的电脉冲改变其电阻的非易失性存储元件，包括用于执行第一写入的第一写入电路（106），其中 将第一电脉冲施加到非易失性存储元件，以将非易失性存储元件的电阻值从第一电阻值切换到第二电阻值，并将与第一电脉冲极性相反的第二电脉冲施加到非易失性存储元件 存储元件，用于将非易失性存储元件的电阻值从第二电阻值切换到第一电阻值; 以及第二写入电路（108），用于执行第二写入，其中第三电脉冲被施加到非易失性存储元件，以将非易失性存储元件的电阻值从第三电阻值切换到第四电阻值和第四电脉冲 将与第三电脉冲相同的极性相加到非易失性存储元件，以将非易失性存储元件的电阻值从第四电阻值切换到第五电阻值。

公开(公告)号：US20140061579A1

公开(公告)日：2014-03-06

申请号：US13995383

申请日：2012-10-22

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Koji Katayama

IPC分类号： H01L45/00 ,  H01L27/24

CPC分类号： H01L45/145 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/0083 ,  G11C2213/15 ,  H01L27/101 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1625

摘要： A variable resistance nonvolatile memory element includes a first electrode, a second electrode, and a variable resistance layer including: a first oxide layer including a metal oxide having non-stoichiometric composition and including p-type carriers; a second oxide layer located between and in contact with the first oxide layer and a second electrode and including a metal oxide having non-stoichiometric composition and including n-type carriers; an oxygen reservoir region located in the first oxide layer, having no contact with the first electrode, and having an oxygen content atomic percentage higher than that of the first oxide layer; and a local region located in the second oxide layer, having contact with the oxygen reservoir region, and having an oxygen content atomic percentage lower than that of the second oxide layer.

摘要翻译： 可变电阻非易失性存储元件包括第一电极，第二电极和可变电阻层，包括：包含具有非化学计量组成的金属氧化物并包括p型载流子的第一氧化物层; 位于第一氧化物层之间并与第一氧化物层接触的第二氧化物层和第二电极，并且包括具有非化学计量组成并包括n型载体的金属氧化物; 位于所述第一氧化物层中的与第一电极没有接触并且氧含量原子百分比高于第一氧化物层的氧储存区; 以及位于所述第二氧化物层中的与氧储存区接触并且氧含量原子百分比低于第二氧化物层的原子百分比的局部区域。

公开(公告)号：US08339835B2

公开(公告)日：2012-12-25

申请号：US13000243

申请日：2010-04-22

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0002 ,  G11C2213/72 ,  H01L27/24

摘要： A nonvolatile memory element includes a current controlling element having a non-linear current-voltage characteristic, a resistance variable element which changes reversibly between a low-resistance state and a high-resistance state in which a resistance value of the resistance variable element is higher than a resistance value of the resistance variable element in the low-resistance state, in response to voltage pulses applied, and a fuse. The current controlling element, the resistance variable element and the fuse are connected in series, and the fuse is configured to be blown when the current controlling element is substantially short-circuited.

摘要翻译： 非易失性存储元件包括具有非线性电流 - 电压特性的电流控制元件，在电阻可变元件的电阻值较高的低电阻状态与高电阻状态之间可逆地改变的电阻可变元件 比电阻可变元件在低电阻状态下的电阻值，响应于施加的电压脉冲和保险丝。 电流控制元件，电阻可变元件和保险丝串联连接，并且当电流控制元件基本上短路时，保险丝被配置为被熔断。

公开(公告)号：US20120319072A1

公开(公告)日：2012-12-20

申请号：US13580401

申请日：2011-02-23

申请人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

发明人： Zhiqiang Wei ,  Takeshi Takagi ,  Mitsuteru Iijima

IPC分类号： H01L47/00 ,  H01L21/02

CPC分类号： H01L45/1226 ,  G11C13/0002 ,  G11C2213/77 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/08 ,  H01L45/146 ,  H01L45/1633

摘要： A manufacturing method for manufacturing, with a simple process, a non-volatile memory apparatus having a stable memory performance includes: (a) forming a stacking-structure body above a substrate by alternately stacking conductive layers comprising a transition metal and interlayer insulating films comprising an insulating material; (b) forming a contact hole penetrating through the stacking-structure body to expose part of each of the conductive layers; (c) forming variable resistance layers by oxidizing the part of each of the conductive layers, the part being exposed in the contact hole, and each of the variable resistance layers having a resistance value that reversibly changes according to an application of an electric signal; and (d) forming a pillar electrode in the contact hole by embedding a conductive material in the contact hole, the pillar electrode being connected to each of the variable resistance layers.

摘要翻译： 一种以简单的工艺制造具有稳定的存储性能的非易失性存储装置的制造方法包括：（a）通过交替堆叠包括过渡金属和层间绝缘膜的导电层，在衬底上形成堆叠结构体，所述导电层包括： 绝缘材料; （b）形成穿过堆叠结构体的接触孔，以暴露出每个导电层的部分; （c）通过氧化每个导电层的一部分形成可变电阻层，该部分暴露在接触孔中，并且每个可变电阻层具有根据电信号的应用可逆地改变的电阻值; 和（d）通过在接触孔中埋设导电材料而在接触孔中形成柱状电极，该柱状电极与各可变电阻层连接。

公开(公告)号：US08320159B2

公开(公告)日：2012-11-27

申请号：US12993706

申请日：2010-03-15

申请人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

发明人： Zhiqiang Wei ,  Ryotaro Azuma ,  Takeshi Takagi ,  Mitsuteru Iijima ,  Yoshihiko Kanzawa

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C2213/75 ,  G11C2213/79 ,  H01L27/115 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1625

摘要： Each of memory cells (MC) includes one transistor and one resistance variable element. The transistor includes a first main terminal, a second main terminal and a control terminal. The resistance variable element includes a first electrode, a second electrode and a resistance variable layer provided between the first electrode and the second electrode. A first main terminal of one of two adjacent memory cells is connected to a second main terminal of the other memory cell, to form a series path (SP) sequentially connecting main terminals of the plurality of memory cells in series. Each of the memory cells is configured such that the control terminal is a part of a first wire (WL) associated with the memory cell or is connected to the first wire associated with the memory cell, the second electrode is a part of a second wire (SL) associated with the memory cell or is connected to the second wire associated with the memory cell; and the first electrode is a part of a series path (SP) associated with the memory cell or is connected to the series path associated with the memory cell.

摘要翻译： 每个存储单元（MC）包括一个晶体管和一个电阻可变元件。 晶体管包括第一主端子，第二主端子和控制端子。 电阻可变元件包括设置在第一电极和第二电极之间的第一电极，第二电极和电阻变化层。 两个相邻存储单元之一的第一主端子连接到另一个存储单元的第二主端子，以形成串联连接多个存储单元的主端子的串行路径（SP）。 每个存储器单元被配置为使得控制端子是与存储器单元相关联的第一布线（WL）的一部分或者连接到与存储单元相关联的第一布线，第二电极是第二布线 （SL），或者连接到与存储器单元相关联的第二线; 并且第一电极是与存储器单元相关联的或连接到与存储器单元相关联的串联路径的串联路径（SP）的一部分。