公开(公告)号：US11336552B2

公开(公告)日：2022-05-17

申请号：US16795309

申请日：2020-02-19

申请人： Hewlett Packard Enterprise Development LP

发明人： Anuradha Arabinda Bose

IPC分类号： H04L43/10 ,  H04L41/0631 ,  H04L43/50 ,  G06F9/455 ,  H04L43/0817

摘要： A system to facilitate troubleshooting a hardware device in a network switching fabric is described. The system includes a processor and a machine readable medium storing instructions that, when executed, cause the processor to receive a message from a hardware device indicating that a problem has been detected at the device, perform a troubleshooting operation to determine the problem at the hardware device and generate a report including the results of the troubleshooting operation.

公开(公告)号：US11303923B2

公开(公告)日：2022-04-12

申请号：US16437158

申请日：2019-06-11

申请人： Intel Corporation

发明人： Jill Boyce ,  Zhipin Deng ,  Lidong Xu

IPC分类号： H04N19/523 ,  H04N19/573 ,  H04N19/543 ,  H04N19/52 ,  H04N19/597

摘要： Embodiments are generally directed to affine motion compensation for current picture referencing. An embodiment of an apparatus includes one or more processors for processing of data; a memory for storage of data including video data; and an encoder for encoding of video data to generate encoded video data, wherein the encoder includes a component to provide affine motion compensation for current picture references in the video data.

公开(公告)号：US11303429B2

公开(公告)日：2022-04-12

申请号：US16455950

申请日：2019-06-28

申请人： Intel Corporation

发明人： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC分类号： H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

摘要： In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.

公开(公告)号：US11276308B2

公开(公告)日：2022-03-15

申请号：US16681060

申请日：2019-11-12

申请人： Locix Inc.

发明人： Teymur Bakhishev ,  Vivek Subramanian ,  Vikram Pavate ,  Tommi Ylamurto

IPC分类号： G08G1/14 ,  G06K9/00 ,  G06N20/00 ,  G06K9/62 ,  H04B17/27 ,  H04B17/318 ,  H04B17/23

摘要： Systems and methods for using radio frequency signals and sensors to monitor environments (e.g., indoor building and adjacent outdoor environments) are disclosed herein. In one embodiment, a system for providing a wireless asymmetric network comprises a hub having one or more processing units and at least one antenna for transmitting and receiving radio frequency (RF) communications in the wireless asymmetric network and a plurality of sensor nodes each having a wireless device with a transmitter and a receiver to enable bi-directional RF communications with the hub in the wireless asymmetric network. The one or more processing units of the hub are configured to determine localization of the plurality of sensor nodes within the wireless asymmetric network, to monitor loading zones and adjacent regions within a building based on receiving information from at least two sensor nodes, and to determine for each loading zone whether a vehicle currently occupies the loading zone.

公开(公告)号：US11270406B2

公开(公告)日：2022-03-08

申请号：US17099118

申请日：2020-11-16

申请人： Intel Corporation

发明人： Murali Ramadoss ,  Balaji Vembu ,  Eric C. Samson ,  Kun Tian ,  David J. Cowperthwaite ,  Altug Koker ,  Zhi Wang ,  Joydeep Ray ,  Subramaniam M. Maiyuran ,  Abhishek R. Appu

IPC分类号： G06F9/48 ,  G06T1/20 ,  G06F9/50 ,  G06F9/38

摘要： Embodiments described herein provide techniques enable a compute unit to continue processing operations when all dispatched threads are blocked. One embodiment provides for a method comprising executing multiple concurrent threads on a processing resource of a graphics processor, during execution, detecting that each of the multiple concurrent threads of the processing resource are blocked from execution, selecting a victim thread from the multiple concurrent threads, and suspending the victim thread. The thread state is stored to a thread scratch space in memory along with a blocking event associated with the victim thread.

公开(公告)号：US11270201B2

公开(公告)日：2022-03-08

申请号：US15859180

申请日：2017-12-29

申请人： Intel Corporation

发明人： Srinivas Sridharan ,  Karthikeyan Vaidyanathan ,  Dipankar Das ,  Chandrasekaran Sakthivel ,  Mikhail E. Smorkalov

IPC分类号： G06N3/08 ,  G06F9/50 ,  G06N3/04 ,  G06N3/063 ,  G06N7/00

摘要： Embodiments described herein provide a system to configure distributed training of a neural network, the system comprising memory to store a library to facilitate data transmission during distributed training of the neural network; a network interface to enable transmission and receipt of configuration data associated with a set of worker nodes, the worker nodes configured to perform distributed training of the neural network; and a processor to execute instructions provided by the library, the instructions to cause the processor to create one or more groups of the worker nodes, the one or more groups of worker nodes to be created based on a communication pattern for messages to be transmitted between the worker nodes during distributed training of the neural network.

公开(公告)号：US11232536B2

公开(公告)日：2022-01-25

申请号：US16791514

申请日：2020-02-14

申请人： Intel Corporation

发明人： Adam T. Lake ,  Guei-Yuan Lueh ,  Balaji Vembu ,  Murali Ramadoss ,  Prasoonkumar Surti ,  Abhishek R. Appu ,  Altug Koker ,  Subramaniam M. Maiyuran ,  Eric C. Samson ,  David J. Cowperthwaite ,  Zhi Wang ,  Kun Tian ,  David Puffer ,  Brian T. Lewis

IPC分类号： G06T1/60 ,  G06T1/20 ,  G06F8/41 ,  G06F12/0862

摘要： An apparatus to facilitate data prefetching is disclosed. The apparatus includes a memory, one or more execution units (EUs) to execute a plurality of processing threads and prefetch logic to prefetch pages of data from the memory to assist in the execution of the plurality of processing threads.

公开(公告)号：US11222392B2

公开(公告)日：2022-01-11

申请号：US16531763

申请日：2019-08-05

申请人： Intel Corporation

发明人： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L. Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC分类号： G06T1/20 ,  G06T1/60 ,  G09G5/36 ,  G06F3/06 ,  G06N3/08 ,  G06F3/14 ,  G06N3/04 ,  G06N3/063 ,  G09G5/00

摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a memory device including a first integrated circuit (IC) including a plurality of memory channels and a second IC including a plurality of processing units, each coupled to a memory channel in the plurality of memory channels.

公开(公告)号：US11218320B2

公开(公告)日：2022-01-04

申请号：US16455908

申请日：2019-06-28

申请人： Intel Corporation

发明人： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC分类号： H04L29/06 ,  H04L9/32 ,  H04L9/08

摘要： In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US11216296B2

公开(公告)日：2022-01-04

申请号：US16387490

申请日：2019-04-17

申请人： Hewlett Packard Enterprise Development LP

发明人： Balaji Ramamoorthi ,  Siva Subramaniam Manickam ,  Vinnarasu Ganesan ,  Thavamaniraja Sakthivel

IPC分类号： G06F9/455

摘要： Virtual machine images available across a plurality of cloud networks may be identified. A catalog of the virtual machine images may be generated. The catalog may comprise, for each virtual machine image, a mapping information, comprising: a name of a virtual machine image, a name of a virtual machine instance based on the virtual machine image, a name of a cloud network providing the virtual machine image, a cost of deploying the virtual machine instance on the cloud network, a tag identifying a feature of the virtual machine image, and an identification tag assigned to the virtual machine image. For a given virtual machine instance, the catalog of the virtual machine images may be analyzed to identify a least cost cloud network.